公开(公告)号：US06340601B1

公开(公告)日：2002-01-22

申请号：US09476237

申请日：1999-12-30

申请人： Thomas F. Curran, Jr. ,  Timothy C. Krywanczyk ,  Michael S. Lube ,  Matthew D. Moon ,  Rock Nadeau ,  Clark D. Reynolds ,  Dean A. Schaffer ,  Joel M. Sharrow ,  Paul H. Smith, Jr. ,  David C. Thomas ,  Eric J. White ,  Kenneth H. Yao

发明人： Thomas F. Curran, Jr. ,  Timothy C. Krywanczyk ,  Michael S. Lube ,  Matthew D. Moon ,  Rock Nadeau ,  Clark D. Reynolds ,  Dean A. Schaffer ,  Joel M. Sharrow ,  Paul H. Smith, Jr. ,  David C. Thomas ,  Eric J. White ,  Kenneth H. Yao

IPC分类号： H01L214763

CPC分类号： H01L21/76892

摘要： A method of reworking copper metallurgy on semiconductor devices which includes selective removal of insulator, selective removal of copper, non-selective removal of copper and insulator followed by the redeposition of an insulating copper barrier layer and at least one metallurgical interconnect layer.

摘要翻译： 一种对半导体器件上的铜冶炼进行再加工的方法，包括绝缘体的选择性去除，铜的选择性去除，铜和绝缘体的非选择性去除，然后再沉积绝缘铜阻挡层和至少一个冶金互连层。

公开(公告)号：US5523253A

公开(公告)日：1996-06-04

申请号：US389529

申请日：1995-02-16

申请人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

发明人： Richard A. Gilmour ,  Thomas J. Hartswick ,  David C. Thomas ,  Ronald R. Uttecht ,  Erick G. Walton

IPC分类号： H01L23/62 ,  H01L21/82

CPC分类号： H01L23/62 ,  H01L2924/0002

摘要： The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures.Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

摘要翻译： 本公开提出了一种改进的集成电路，其中与保险丝相邻的电路元件由位于保险丝附近的屏障保护。 在改进的集成电路中，阻挡层是非易碎的，高熔点结构掩埋在钝化层中，覆盖包含保险丝的布线层，并且位于布线层结构中的熔丝和相邻的电路元件之间。 还教导了一种保护靠近熔丝的电路元件的方法，包括以下步骤：在其中具有有源区的半导体器件的表面上沉积绝缘层，在所述层中形成多个保险丝和电路元件，将所述保险丝和元件涂覆 第二绝缘层，图案化所述第二绝缘层以在每个所述保险丝和任何相邻的熔丝或电路元件之间形成槽，以及在所述槽中沉积高熔点和非易碎材料。

公开(公告)号：US20120102885A1

公开(公告)日：2012-05-03

申请号：US13060754

申请日：2009-10-13

申请人： Phillip Neal Sharp ,  Sven Newman ,  David C. Thomas ,  Anita G. Mooy

发明人： Phillip Neal Sharp ,  Sven Newman ,  David C. Thomas ,  Anita G. Mooy

IPC分类号： B65B3/02

CPC分类号： B65B43/02 ,  B05C17/00583 ,  B65B3/02 ,  B65B7/02 ,  B65B51/02 ,  B65B61/202 ,  B65B61/24 ,  B65B69/005 ,  B65D35/10 ,  B65D35/28 ,  B65D75/28 ,  B65D75/30 ,  B65D75/5811

摘要： A method of forming and filling a pouch, comprises forming opposing walls of a film; sealing the opposing walls of film together to form at least one pouch; filling an interior section of the at least one pouch through an opening in an upper portion of the at least one pouch with a flowable material; forming a top sealed expressing-shaped region to close the opening in the at least one pouch; and cradling the pouch with a foldable flat that is more rigid than the pouch that can be folded or rolled to compress the pouch to express the flowable material through the expressing shaped region.

摘要翻译： 一种形成和填充袋的方法，包括形成膜的相对壁; 将膜的相对的壁密封在一起以形成至少一个袋; 通过具有可流动材料的所述至少一个袋的上部中的开口填充所述至少一个袋的内部部分; 形成顶部密封的表面形状区域以封闭所述至少一个袋子中的开口; 并且用可折叠或可滚动以压缩袋以便通过表达成形区域表达可流动材料的小袋可折叠的扁平物包起来。

公开(公告)号：US20090230555A1

公开(公告)日：2009-09-17

申请号：US12049698

申请日：2008-03-17

申请人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

发明人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53223 ,  H01L23/5329 ,  H01L2221/1078 ,  H01L2924/0002 ,  H01L2924/00

摘要： An underlying interconnect level containing underlying W vias embedded in a dielectric material layer are formed on a semiconductor substrate. A metallic layer stack comprising, from bottom to top, a low-oxygen-reactivity metal layer, a bottom transition metal layer, a bottom transition metal nitride layer, an aluminum-copper layer, an optional top transition metal layer, and a top transition metal nitride layer. The metallic layer stack is lithographically patterned to form at least one aluminum-based metal line, which constitutes a metal interconnect structure. The low-oxygen-reactivity metal layer enhances electromigration resistance of the at least one aluminum-based metal line since formation of compound between the bottom transition metal layer and the dielectric material layer is prevented by the low-oxygen-reactivity metal layer, which does not interact with the dielectric material layer.

摘要翻译： 在半导体衬底上形成包含埋在电介质材料层中的底层W通孔的底层互连层。 一种金属层堆叠，包括从底部到顶部的低氧反应性金属层，底部过渡金属层，底部过渡金属氮化物层，铝 - 铜层，任选的顶部过渡金属层和顶部过渡层 金属氮化物层。 金属层堆叠被光刻图案化以形成至少一个构成金属互连结构的铝基金属线。 低氧反应性金属层由于通过低氧反应性金属层防止了底部过渡金属层和电介质材料层之间的化合物的形成，因此提高了至少一种铝基金属线的电迁移率 不与介电材料层相互作用。

公开(公告)号：US06982227B2

公开(公告)日：2006-01-03

申请号：US10687294

申请日：2003-10-16

申请人： Edward C. Cooney, III ,  Robert M. Geffken ,  Vincent J. McGahay ,  William T. Motsiff ,  Mark P. Murray ,  Amanda L. Piper ,  Anthony K. Stamper ,  David C. Thomas ,  Christy S. Tyberg ,  Elizabeth T. Webster

发明人： Edward C. Cooney, III ,  Robert M. Geffken ,  Vincent J. McGahay ,  William T. Motsiff ,  Mark P. Murray ,  Amanda L. Piper ,  Anthony K. Stamper ,  David C. Thomas ,  Christy S. Tyberg ,  Elizabeth T. Webster

IPC分类号： H01L21/302

CPC分类号： H01L21/76808 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76892 ,  H01L23/525 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1031 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of reworking BEOL (back end of a processing line) metallization levels of damascene metallurgy comprises forming a plurality of BEOL metallization levels over a substrate, forming line and via portions in the BEOL metallization levels, selectively removing at least one of the BEOL metallization levels to expose the line and via portions, and replacing the removed BEOL metallization levels with at least one new BEOL metallization level, wherein the BEOL metallization levels comprise a first dielectric layer and a second dielectric layer, and wherein the first dielectric layer comprising a lower dielectric constant material than the second dielectric layer.

摘要翻译： 一种重新加工BEOL（处理线的后端）金刚石冶金的金​​属化水平的方法包括在衬底上形成多个BEOL金属化水平，在BEOL金属化水平中形成线和通孔部分，选择性地去除BEOL金属化中的至少一个 以暴露线路和通孔部分，并且用至少一个新的BEOL金属化水平替换去除的BEOL金属化水平，其中BEOL金属化水平包括第一介电层和第二介电层，并且其中第一介电层包括下部 介电常数材料比第二介电层。

公开(公告)号：US4746621A

公开(公告)日：1988-05-24

申请号：US938498

申请日：1986-12-05

申请人： David C. Thomas ,  S. Simon Wong

发明人： David C. Thomas ,  S. Simon Wong

IPC分类号： H01L21/3205 ,  H01L21/768 ,  H01L21/425 ,  H01L21/443

CPC分类号： H01L21/76867 ,  H01L21/32051 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76876 ,  H01L21/76879

摘要： A planar interconnect using selective deposition of a refractory metal such as tungsten into oxide channels is disclosed. A layer of silicon dioxide as thick as the desired tungsten interconnect is placed on the surface of a substrate such as an integrated circuit wafer. Thereafter, a layer of silicon nitride about 100 nm thick is formed on the silicon dioxide. Channels are formed in the silicon dioxide by patterning and etching the composite dielectric layers. After the photoresist is removed, silicon or tungsten atoms at 40 KeV are implanted in the silicon dioxide channels, the silicon nitride acting as a mask. Typically, a dosage as high as 1.times.10.sup.17 cm.sup.-2 is used. The silicon or tungsten implant allows seeding of the tungsten or other refractory metal. The silicon nitride mask is selectively removed by a hot phosphoric acid solution, and a metal film is then selectively deposited to fill the channels in the silicon dioxide layer, which then forms a level of interconnects. The process is repeated to form vias and subsequent levels of interconnects.

摘要翻译： 公开了使用将难熔金属如钨选择性沉积到氧化物通道中的平面互连。 将诸如所需钨互连的厚度的二氧化硅层放置在诸如集成电路晶片的衬底的表面上。 此后，在二氧化硅上形成约100nm厚的氮化硅层。 通过图案化和蚀刻复合电介质层，在二氧化硅中形成沟道。 在除去光致抗蚀剂之后，将40KeV的硅或钨原子注入到二氧化硅通道中，氮化硅用作掩模。 通常，使用高达1×10 17 cm -2的剂量。 硅或钨植入物允许接合钨或其它难熔金属。 通过热磷酸溶液选择性地除去氮化硅掩模，然后选择性地沉积金属膜以填充二氧化硅层中的通道，然后形成一定程度的互连。 重复该过程以形成通孔和随后的互连级别。

公开(公告)号：US4446519A

公开(公告)日：1984-05-01

申请号：US266724

申请日：1981-05-26

申请人： David C. Thomas

发明人： David C. Thomas

IPC分类号： G06F21/00 ,  G06F1/00

CPC分类号： G06F21/123 ,  G06F21/125 ,  G06F2211/007 ,  G06F2221/2153

摘要： Security for computer software is achieved by providing each purchaser of a software package with an electronic security device which must be operatively connected to the purchaser's computer. The software sends coded interrogation signals to the electronic security device which processes the interrogation signals and transmits coded response signals to the software. The program will not be executed unless the software recognizes the response signals according to preselected security criteria.

摘要翻译： 通过为软件包的每个购买者提供必须可操作地连接到购买者的计算机的电子安全装置来实现计算机软件的安全性。 软件将编码的询问信号发送到处理询问信号的电子安全装置，并向软件发送编码的响应信号。 除非软件根据预先选择的安全标准识别响应信号，否则程序将不会被执行。

公开(公告)号：US08003536B2

公开(公告)日：2011-08-23

申请号：US12552641

申请日：2009-09-02

申请人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

发明人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76858 ,  H01L2221/1078

摘要： A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

公开(公告)号：US07977053B2

公开(公告)日：2011-07-12

申请号：US11609436

申请日：2006-12-12

申请人： David C. Thomas

发明人： David C. Thomas

IPC分类号： C12Q1/68 ,  C12P19/34 ,  C07H21/02 ,  C07H21/04

CPC分类号： C12Q1/6844 ,  C12Q2537/143 ,  C12Q2525/307 ,  C12Q2521/101

摘要： The present invention provides methods and kits for the rapid exponential amplification of nucleic acid molecules using a padlock probe. The present invention improves upon the existing methods for amplifying padlock probes by eliminating or delaying the appearance of artifact products that cause false positive results, and also increase the sensitivity and speed of the assay. Further provided are nucleic acid amplification primers containing non-informative base analogs.

摘要翻译： 本发明提供了使用挂锁探针快速指数扩增核酸分子的方法和试剂盒。 本发明通过消除或延迟造成假阳性结果的伪影产品的外观来改进现有的挂锁探针的方法，并且还提高了测定的灵敏度和速度。 还提供含有非信息性碱基类似物的核酸扩增引物。

公开(公告)号：US20100237503A1

公开(公告)日：2010-09-23

申请号：US12552641

申请日：2009-09-02

申请人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

发明人： Jonathan D. Chapple-Sokol ,  Daniel A. Delibac ,  Zhong-Xiang He ,  Tom C. Lee ,  William J. Murphy ,  Timothy D. Sullivan ,  David C. Thomas ,  Daniel S. Vanslette

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/32051 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76858 ,  H01L2221/1078

摘要： A vertical metallic stack, from bottom to top, of an elemental metal liner, a metal nitride liner, a Ti liner, an aluminum portion, and a metal nitride cap, is formed on an underlying metal interconnect structure. The vertical metallic stack is annealed at an elevated temperature to induce formation of a TiAl3 liner by reaction of the Ti liner with the material of the aluminum portion. The material of the TiAl3 liner is resistant to electromigration, thereby providing enhanced electromigration resistance to the vertical metallic stack comprising the elemental metal liner, the metal nitride liner, the TiAl3 liner, the aluminum portion, and the metal nitride cap. The effect of enhanced electromigration resistance may be more prominent in areas in which the metal nitride cap suffers from erosion during processing.

摘要翻译： 在下面的金属互连结构上形成由元素金属衬垫，金属氮化物衬垫，Ti衬垫，铝部分和金属氮化物盖的从底部到顶部的垂直金属堆叠。 垂直金属叠层在升高的温度下退火，以通过Ti衬垫与铝部分的材料反应而引起TiAl 3衬层的形成。 TiAl 3衬垫的材料对电迁移是耐受的，从而对包括元素金属衬垫，金属氮化物衬垫，TiAl 3衬里，铝部分和金属氮化物盖的垂直金属堆叠提供增强的电迁移阻力。 在金属氮化物盖在加工过程中遭受侵蚀的区域中，增强的耐电迁移性的作用可能更为突出。