-
公开(公告)号：US06083806A
公开(公告)日：2000-07-04
申请号：US110352
申请日：1998-07-06
IPC分类号： G03F9/00 , H01L23/544 , H01L21/76
CPC分类号： G03F9/708 , G03F9/7084 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002
摘要： An alignment mark (51) is formed on the surface (64) of a silicon carbide substrate (50). The alignment mark (51) is used to reflect a light signal (72) to determine the proper position for the silicon carbide substrate (50). The materials that are used to form the alignment mark (51) can be used to form an alignment mark on any transparent or semi-transparent substrate and will maintain physical integrity through very high temperature processing steps.
摘要翻译： 在碳化硅衬底（50）的表面（64）上形成对准标记（51）。 对准标记（51）用于反射光信号（72）以确定碳化硅衬底（50）的适当位置。 用于形成对准标记（51）的材料可以用于在任何透明或半透明基材上形成对准标记，并且将通过非常高的温度处理步骤来保持物理完整性。
-
公开(公告)号：US06630746B1
公开(公告)日：2003-10-07
申请号：US09566961
申请日：2000-05-09
IPC分类号： H01L2348
CPC分类号： G03F9/7076 , G03F9/7069 , H01L2223/54426
摘要： An alignment mark (51) is formed on the surface (64) of a silicon carbide substrate (50). The alignment mark (51) is used to reflect a light signal (72) to determine the proper position for the silicon carbide substrate (50). The materials that are used to form the alignment mark (51) can be used to form an alignment mark on any transparent or semi-transparent substrate and will maintain physical integrity through very high temperature processing steps.
摘要翻译： 在碳化硅衬底（50）的表面（64）上形成对准标记（51）。 对准标记（51）用于反射光信号（72）以确定碳化硅衬底（50）的适当位置。 用于形成对准标记（51）的材料可以用于在任何透明或半透明基材上形成对准标记，并且将通过非常高的温度处理步骤来保持物理完整性。
-
公开(公告)号：US08946776B2
公开(公告)日：2015-02-03
申请号：US13533610
申请日：2012-06-26
IPC分类号： H01L29/812
CPC分类号： H01L21/28581 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。
-
4.发明授权
公开(公告)号：US6127272A
公开(公告)日：2000-10-03
申请号：US13271
申请日：1998-01-26
申请人： Charles E. Weitzel , Karen E. Moore
发明人： Charles E. Weitzel , Karen E. Moore
IPC分类号： H01L21/027 , H01L21/301 , H01L21/338
CPC分类号： H01L21/0277
摘要： A method of performing electron beam lithography on high resistivity substrates including forming semiconductor material on a high resistivity substrate and etching the semiconductor material to form mesas with electrically interconnecting bridges between the mesas. Semiconductor devices are formed in the mesas employing electron beam lithography and charges generated by the electron beam lithography are dispersed along the interconnecting bridges thereby preventing charge accumulation on the mesas. The bridges are removed by etching or sawing during die separation.
摘要翻译： 一种在高电阻率衬底上执行电子束光刻的方法，包括在高电阻率衬底上形成半导体材料并蚀刻半导体材料以形成台面之间的电互连桥的台面。 使用电子束光刻在台面形成半导体器件，并且通过电子束光刻产生的电荷沿着互连桥分散，从而防止台面上的电荷积累。 在分离模具期间通过蚀刻或锯切来除去桥。
-
公开(公告)号：US5933750A
公开(公告)日：1999-08-03
申请号：US54561
申请日：1998-04-03
IPC分类号： H01L21/762 , H01L21/58
CPC分类号： H01L21/76254 , H01L21/76251 , Y10S438/977
摘要： A method of fabricating a semiconductor device on thinned wide bandgap material including providing a support having a planar surface and a semiconductor substrate. Implanting a layer of ions in the substrate to create a layer of microbubbles defining a thin film having a planar surface and a remaining mass separated by the layer of implanted ions. Intimately contacting the planar surface of the thin film to the planar surface of the support and heating the support and substrate to separate the remaining mass from the thin film. A semiconductor device is formed on the thin film, and the support is thinned.
摘要翻译： 一种在薄的宽带隙材料上制造半导体器件的方法，包括提供具有平坦表面的支撑体和半导体衬底。 在衬底中植入一层离子以产生限定具有平坦表面的薄膜的微泡层和由注入离子层分离的剩余物质。 将薄膜的平坦表面紧密接触支撑体的平面表面，并加热支撑体和基底，以将剩余的质量与薄膜分离。 半导体器件形成在薄膜上，并且支撑体变薄。
-
公开(公告)号：US6002148A
公开(公告)日：1999-12-14
申请号：US497569
申请日：1995-06-30
IPC分类号： H01L21/04 , H01L21/28 , H01L29/24 , H01L29/423 , H01L29/812
CPC分类号： H01L29/1608 , H01L21/0445 , H01L21/0495 , H01L21/2815 , H01L29/42316 , H01L29/66068 , Y10S438/931
摘要： A silicon carbide MESFET (10) is formed to have a source (21) and a drain (22) that are self-aligned to a gate (16) of the MESFET (10). The gate (16) is formed to have a T-shaped structure with a gate-to-source spacer (18) and gate-to-drain spacer (19) along each side of a base of the gate (16). The gate (16) is used as a mask for implanting dopants to form the source (21) and drain (22). A laser annealing is performed after the implantation to activate the dopants. Because the laser annealing is a low temperature operation, the gate (16) is not detrimentally affected during the annealing.
-
公开(公告)号：US5693969A
公开(公告)日：1997-12-02
申请号：US398838
申请日：1995-03-06
IPC分类号： H01L21/28 , H01L21/285 , H01L21/338 , H01L29/08 , H01L29/80 , H01L31/0312
CPC分类号： H01L29/66863 , H01L21/2815 , H01L21/28587 , H01L29/0891
摘要： A lateral MESFET (10,20) utilizes a drain (17) and a source (18) damage termination layer to improve the breakdown voltage of the MESFET (10,20). The source (18) and drain (17) damage termination layers are very shallow to prevent interfering with lateral current flow in the channel layer (12). The source (18) and drain (17) damage termination layers are formed by implanting large inert ions using high implant doses and low implantation energies.
摘要翻译： 横向MESFET（10,20）利用漏极（17）和源极（18）损伤端接层来改善MESFET（10,20）的击穿电压。 源极（18）和漏极（17）损坏终端层非常浅，以防止干扰沟道层（12）中的横向电流。 源（18）和漏极（17）损伤终端层通过使用高注入剂量和低注入能量注入大的惰性离子而形成。
-
公开(公告)号：US5641695A
公开(公告)日：1997-06-24
申请号：US538063
申请日：1995-10-02
申请人： Karen E. Moore , Charles E. Weitzel
发明人： Karen E. Moore , Charles E. Weitzel
IPC分类号： H01L21/04 , H01L29/24 , H01L29/808 , H01L21/265 , H01L21/20
CPC分类号： H01L29/1608 , H01L29/66068 , H01L29/808 , Y10S438/931 , Y10S438/945
摘要： An implant mask (14) and an etch mask (16) are utilized in forming a silicon carbide JFET (10). A source opening (17) and a drain opening (18) are formed in the masks (14,16). The etch mask (16) is removed, and a source area (19) and a drain area 21 are implanted through the openings (17,18) and source and drain contact (23, 24) are formed. A protective layer (26) is used to form source and drain contacts (23,24). A gate contact (27) is utilized to ensure the gate (28) is self-aligned to the gate contact (27).
摘要翻译： 在形成碳化硅JFET（10）中使用注入掩模（14）和蚀刻掩模（16）。 在所述掩模（14,16）中形成有源极开口（17）和排出开口（18）。 去除蚀刻掩模（16），并且通过开口（17,18）注入源极区域（19）和漏极区域21，并且形成源极和漏极接触（23,24）。 保护层（26）用于形成源极和漏极接触（23,24）。 栅极接触（27）用于确保栅极（28）与栅极接触件（27）自对准。
-
公开(公告)号：US20150132932A1
公开(公告)日：2015-05-14
申请号：US14601804
申请日：2015-01-21
IPC分类号： H01L21/285
CPC分类号： H01L21/28581 , H01L21/31111 , H01L21/31116 , H01L29/0615 , H01L29/1029 , H01L29/2003 , H01L29/402 , H01L29/66462 , H01L29/7787 , H01L29/812
摘要： A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The second dielectric layer is patterned such that the first dielectric layer is disposed on the surface of the semiconductor substrate in a second area over the channel.
摘要翻译： 半导体器件包括被配置为包括沟道的半导体衬底，由半导体衬底支撑的栅极以控制通过沟道的电流;由半导体衬底支撑并包括其中设置栅极的开口的第一电介质层，以及 第二电介质层，设置在所述沟道上的第一区域中的所述第一介电层和所述半导体衬底的表面之间。 图案化第二电介质层，使得第一电介质层在通道上的第二区域中设置在半导体衬底的表面上。
-
公开(公告)号：US08592878B2
公开(公告)日：2013-11-26
申请号：US13042948
申请日：2011-03-08
IPC分类号： H01L29/66
CPC分类号： H01L21/28581 , H01L21/28587 , H01L29/0657 , H01L29/2003 , H01L29/42316 , H01L29/432 , H01L29/475 , H01L29/7787
摘要： Embodiments include semiconductor devices with low leakage Schottky contacts. An embodiment is formed by providing a partially completed semiconductor device including a substrate, a semiconductor on the substrate, and a passivation layer on the semiconductor, and using a first mask, locally etching the passivation layer to expose a portion of the semiconductor. Without removing the first mask, a Schottky contact is formed of a first material on the exposed portion of the semiconductor, and the first mask is removed. Using a further mask, a step-gate conductor of a second material electrically coupled to the Schottky contact is formed overlying parts of the passivation layer adjacent to the Schottky contact. By minimizing the process steps between opening the Schottky contact window in the passivation layer and forming the Schottky contact material in this window, the gate leakage of a resulting field effect device having a Schottky gate may be substantially reduced.
摘要翻译： 实施例包括具有低泄漏肖特基接触的半导体器件。 通过提供部分完成的半导体器件形成一个实施例，该半导体器件包括衬底，衬底上的半导体和半导体上的钝化层，并且使用第一掩模，局部蚀刻钝化层以暴露半导体的一部分。 在不去除第一掩模的情况下，在半导体的暴露部分上由第一材料形成肖特基接触，并且去除第一掩模。 使用另外的掩模，电耦合到肖特基接触的第二材料的阶梯栅导体形成在与肖特基接触相邻的钝化层的部分上。 通过最小化打开钝化层中的肖特基接触窗口并在该窗口中形成肖特基接触材料之间的工艺步骤，可以显着减少所得到的具有肖特基栅极的场效应器件的栅极泄漏。
-
-
-
-
-
-
-
-
-
搜索结果
23 条记录 (耗时 0.032 秒)
