公开(公告)号：US08659954B1

公开(公告)日：2014-02-25

申请号：US13548470

申请日：2012-07-13

申请人： Derric Lewis ,  Shane Hollmer ,  Vasudevan Gopalakrishnan ,  John Dinh ,  Foroozan Sarah Koushan ,  Juan Pablo Saenz Echeverry

发明人： Derric Lewis ,  Shane Hollmer ,  Vasudevan Gopalakrishnan ,  John Dinh ,  Foroozan Sarah Koushan ,  Juan Pablo Saenz Echeverry

IPC分类号： G11C7/00

CPC分类号： G11C13/0069 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0033 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0092

摘要： Structures and methods for controlling operation of a programmable impedance element are disclosed herein. In one embodiment, a method of controlling a programmable impedance element can include: (i) receiving a program or erase command to be executed on the programmable impedance element; (ii) selecting an operation algorithm for executing the command, where the operation algorithm is selected from among a plurality of operation algorithms by decoding at least two bits stored in a register; (iii) determining, using the register, a plurality of option variables for the selected operation algorithm, where the option variables are used to set conditions for one or more of a plurality of program and erase operations of the selected operation algorithm; and (iv) executing the command on the programmable impedance element by performing the one or more of the plurality of program and erase operations of the selected operation algorithm.

摘要翻译： 本文公开了用于控制可编程阻抗元件的操作的结构和方法。 在一个实施例中，控制可编程阻抗元件的方法可以包括：（i）接收要在可编程阻抗元件上执行的编程或擦除命令; （ii）选择用于执行命令的操作算法，其中通过解码存储在寄存器中的至少两个比特来从多个操作算法中选择操作算法; （iii）使用所述寄存器确定用于所选择的操作算法的多个选项变量，其中所述选项变量用于设置所选择的操作算法的多个编程和擦除操作中的一个或多个的条件; 以及（iv）通过执行所选择的操作算法的多个编程和擦除操作中的一个或多个来执行在可编程阻抗元件上的命令。

公开(公告)号：US09047948B1

公开(公告)日：2015-06-02

申请号：US13548429

申请日：2012-07-13

申请人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

发明人： John Dinh ,  Nad Edward Gilbert ,  Shane Hollmer ,  Derric Lewis ,  John Ross Jameson ,  Daniel C. Wang ,  Juan Pablo Saenz Echeverry

IPC分类号： G11C11/00 ,  G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/5614 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0011 ,  G11C13/0021 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0097

摘要： Structures and methods for control of an operating window of a programmable impedance element are disclosed herein. In one embodiment, a semiconductor memory device can include: (i) a memory array having a programmable impedance element; (ii) a register configured to be programmed with data that represents an erase verify value, a program verify value, and a read trip point resistance value, for the memory array; (iii) a controller configured to determine a mode of operation for the memory array; (iv) a register access circuit configured to read the register to obtain data that corresponds to the mode of operation; and (v) a voltage generator configured to generate a reference voltage based on the register data, where the reference voltage is used to perform an operation on the programmable impedance element corresponding to the mode of operation.

摘要翻译： 本文公开了用于控制可编程阻抗元件的操作窗口的结构和方法。 在一个实施例中，半导体存储器件可以包括：（i）具有可编程阻抗元件的存储器阵列; （ii）配置为对存储器阵列编程的表示擦除验证值，程序验证值和读取跳变点电阻值的寄存器; （iii）控制器，被配置为确定所述存储器阵列的操作模式; （iv）寄存器访问电路，被配置为读取所述寄存器以获得对应于所述操作模式的数据; 以及（v）电压发生器，被配置为基于所述寄存器数据产生参考电压，其中所述参考电压用于对与所述操作模式相对应的所述可编程阻抗元件执行操作。

公开(公告)号：US06510082B1

公开(公告)日：2003-01-21

申请号：US09999869

申请日：2001-10-23

申请人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

发明人： Binh Q. Le ,  Pau-Ling Chen ,  Michael A. Van Buskirk ,  Santosh K. Yachareni ,  Michael S. C. Chung ,  Kazuhiro Kurihara ,  Shane Hollmer

IPC分类号： G11C1604

CPC分类号： G11C16/0491 ,  G11C16/28

摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.

摘要翻译： 公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。 该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线， 其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。 该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流 在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

公开(公告)号：US06472898B1

公开(公告)日：2002-10-29

申请号：US09718986

申请日：2000-11-22

申请人： Shane Hollmer ,  Santosh Yachareni

发明人： Shane Hollmer ,  Santosh Yachareni

IPC分类号： G01R3126

CPC分类号： G01R31/31924

摘要： A method and system for testing a semiconductor memory device applies defined test voltages to a semiconductor memory device in a manner that minimizes a time lapse during shifting from one voltage level to another or one voltage range to another. The system includes registers for storing codewords. Each codeword represents a discrete voltage level. The registers have inputs and outputs. Digital-to-analog converters are coupled to the outputs of the registers for converting a codeword into a corresponding analog voltage with a discrete voltage level. A multiplexer derives a test output voltage from the analog voltage, an external voltage, or both. A mode controller controls the multiplexer to derive the test output voltage. The test output voltage is compliant with defined voltage ranges associated with corresponding modes.

摘要翻译： 用于测试半导体存储器件的方法和系统以将从一个电压电平转换到另一个电压范围或一个电压范围之间的时间流逝最小化的方式将限定的测试电压施加到半导体存储器件。 该系统包括用于存储码字的寄存器。 每个码字表示离散电压电平。 寄存器有输入和输出。 数模转换器耦合到寄存器的输出，用于将码字转换成具有离散电压电平的对应模拟电压。 多路复用器从模拟电压，外部电压或两者获得测试输出电压。 模式控制器控制多路复用器导出测试输出电压。 测试输出电压符合与相应模式相关联的定义电压范围。

公开(公告)号：US06240020B1

公开(公告)日：2001-05-29

申请号：US09427406

申请日：1999-10-25

申请人： Andrew Yang ,  Shane Hollmer ,  Pau-Ling Chen

发明人： Andrew Yang ,  Shane Hollmer ,  Pau-Ling Chen

IPC分类号： G11C1606

CPC分类号： G11C16/24

摘要： A flash memory device includes an array of core cell blocks and page buffers with supporting input/output circuitry. The flash memory device, in addition, contains a method for shielding the bitline for a precharging scheme in which the bitline line of each page buffer is charged prior to the sensing/evaluation cycle of a particular memory element in each core cell block. The precharging scheme increases the speed of response in retrieving information from each core cell block because the bitline line is charged to a predetermined voltage prior to accessing the bitline. The bitline shielding method increases the speed of response further by shielding the effects of neighboring bitlines from each other during the evaluation cycle. The shielding method includes charging different bitlines to preset voltages and then maintaining the preset voltages on a set of the bitlines over the evaluation cycle. The preset voltages are maintained on those bitlines not connected with memory elements undergoing evaluation. The shielding method also includes grounding a latch contained in page buffers connected with the bitlines of memory elements undergoing evaluation prior to the evaluation cycle.

摘要翻译： 闪存器件包括核心单元块阵列和具有支持输入/输出电路的页缓冲器。 另外，闪速存储器件包含用于屏蔽预充电方案的位线的方法，其中在每个核心单元块中的特定存储器元件的感测/评估周期之前，每个页缓冲器的位线被充电。 预充电方案增加了从每个核心单元块检索信息时的响应速度，因为位线在访问位线之前被充电到预定电压。 位线屏蔽方法通过在评估周期期间屏蔽相邻位线的影响进一步增加响应速度。 屏蔽方法包括将不同的位线充电到预设电压，然后在评估周期内将预设电压保持在一组位线上。 在与正在进行评估的存储器元件未连接的那些位线上保持预设电压。 屏蔽方法还包括将与在评估周期之前进行评估的存储器元件的位线连接的页缓冲器中的锁存器接地。

公开(公告)号：US5521867A

公开(公告)日：1996-05-28

申请号：US160057

申请日：1993-12-01

申请人： Jian Chen ,  Lee E. Cleveland ,  Shane Hollmer ,  Ming-Sang Kwan ,  David Liu ,  Nader Radjy

发明人： Jian Chen ,  Lee E. Cleveland ,  Shane Hollmer ,  Ming-Sang Kwan ,  David Liu ,  Nader Radjy

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： G11C16/3409 ,  G11C16/16 ,  G11C16/3404

摘要： A flash EPROM circuit for providing a tight erase threshold voltage distribution. The circuit includes an array of memory cells having gates, sources and drains. Bit lines are coupled to the drains of a column of cells in the memory array. A plurality of word lines are each coupled to the gates of a row of cells in the memory array. A first voltage source is coupled to the bit lines to converge threshold voltages of erased memory cells. A second voltage source is coupled to the word lines to control the threshold voltages of the erased memory cells.

摘要翻译： 用于提供紧密擦除阈值电压分布的闪速EPROM电路。 该电路包括具有门，源和漏极的存储器单元的阵列。 位线耦合到存储器阵列中的一列单元的漏极。 多个字线各自耦合到存储器阵列中的一行单元格的栅极。 第一电压源耦合到位线以会聚被擦除的存储器单元的阈值电压。 第二电压源耦合到字线以控制擦除的存储器单元的阈值电压。

公开(公告)号：US06222768B1

公开(公告)日：2001-04-24

申请号：US09557832

申请日：2000-04-26

申请人： Shane Hollmer ,  Pau-Ling Chen

发明人： Shane Hollmer ,  Pau-Ling Chen

IPC分类号： G11C1604

CPC分类号： G11C16/28 ,  G11C16/0491 ,  G11C16/3436 ,  G11C16/349

摘要： A virtual ground array based flash memory device includes a virtual ground array containing individual memory elements with supporting input/output circuitry. The threshold voltages of the memory elements gradually increase over operating cycles due to trapping of charge in the nitride or oxide, eventually causing errors due to the increase in threshold voltage. Internal routines are necessary to characterize the change in threshold voltages and subsequently modify the comparison circuit supplying the current used to determine whether the memory elements have attained a specific threshold. The method of automatically adjusting the window of the virtual ground array increases endurance and reliability of the virtual ground array and decreases errors caused by the increased threshold voltage.

摘要翻译： 基于虚拟接地阵列的闪存器件包括虚拟接地阵列，其包含具有支持输入/输出电路的各个存储器元件。 存储元件的阈值电压由于在氮化物或氧化物中捕获电荷而在操作周期上逐渐增加，最终由于阈值电压的增加而导致误差。 需要内部程序来表征阈值电压的变化，并且随后修改提供用于确定存储器元件是否达到特定阈值的电流的比较电路。 自动调整虚拟接地阵列的窗口的方法增加了虚拟接地阵列的耐久性和可靠性，并降低了阈值电压增加引起的误差。

公开(公告)号：US6117179A

公开(公告)日：2000-09-12

申请号：US28121

申请日：1998-02-23

申请人： Alexius H. Tan ,  Shane Hollmer ,  Jonathan Su

发明人： Alexius H. Tan ,  Shane Hollmer ,  Jonathan Su

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5022

摘要： An electrical rule check program takes simulation output files as input and performs an electrical rule check on the simulation to determine if any electrical design rules have been violated. The program scans a simulation output file to produce a subcircuit name list, an instance name list, and an internal index list for each subcircuit. If the number of circuit nodes is less than a first predetermined value, a window limit is set to equal the number of nodes times the number of data points. If the number of nodes is greater than the first predetermined value and less than a second predetermined value, then the window limit is set to equal some first predetermined fraction of the product of the number of nodes and the number of data points. If the number of nodes is greater than the second predetermined value, then the window limit is set to equal some second predetermined fraction of the product of the number of nodes and the number of data point, where the second predetermined fraction is less than the first predetermined fraction. The program then scans the simulation output file to produce an indexed node name list and a corresponding indexed voltage list to fill the window. The program performs the electrical rule checks and prints itemized report and statistics information. Each violation type supported by the electrical rule check program according to the present invention has a corresponding own violation output file. Currently supported rule types apply to junction breakdown, punch through, and gate oxide breakdown.

摘要翻译： 电气规则检查程序将模拟输出文件作为输入，并对仿真执行电气规则检查，以确定是否违反了任何电气设计规则。 该程序扫描一个模拟输出文件以产生每个子电路的子电路名称列表，实例名称列表和内部索引列表。 如果电路节点的数量小于第一预定值，则将窗口限制设置为等于节点数乘以数据点数。 如果节点数大于第一预定值且小于第二预定值，则将窗口限制设置为等于节点数和数据点数的乘积的某些第一预定分数。 如果节点数大于第二预定值，则将窗口限制设置为等于节点数和数据点数的乘积的一些第二预定分数，其中第二预定分数小于第一预定分数 预定分数。 程序然后扫描模拟输出文件以产生索引节点名称列表和相应的索引电压列表以填充窗口。 程序执行电气规则检查和打印分项报告和统计信息。 根据本发明的电气规则检查程序支持的每种违规类型都具有相应的自己的违规输出文件。 当前支持的规则类型适用于结点击穿，穿通和栅极氧化物分解。

公开(公告)号：US6055366A

公开(公告)日：2000-04-25

申请号：US28123

申请日：1998-02-23

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Alexius H. Tan

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer ,  Alexius H. Tan

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A two part high voltage check program creates a circuit simulator input file, analyzes the resulting circuit simulator output file for design rule violations, and produces a user report of all violations. The user creates a transistor file which indicates which blocks are to be checked, and optionally specifies individual transistors within the block for checking. The user creates a rule file including rule definitions for the various different types of transistors in the design. The first part generates a print file for input to a circuit simulator. The second part reads the print file, the rule file, and the simulator output file. The second part produces a transistor linked list which is linked to the rule linked list. The second part reads the simulator output file line by line and performs the high voltage electrical rule checks for each transistor for each time step. The second part produces a violation linked lists for each transistor for each violation type. Only tine points representing the beginning or end of a violation sequence are added to the violation linked lists. The second part maintains variables corresponding to each violation type which indicate the maximum violation amount and time for each transistor. The second part produces reports for each transistor's violations, and deallocates the violation linked lists after each transistor has been fully checked. The high voltage rule check program uses dynamic linked list data structures to effectively minimize DRAM utilization at run time.

摘要翻译： 两部分高电压检查程序创建一个电路模拟器输入文件，分析所产生的电路模拟器输出文件以进行设计规则违规，并产生用户报告所有违规。 用户创建一个晶体管文件，该晶体管文件指示要检查的块，并且可选地指定块内的各个晶体管用于检查。 用户创建规则文件，包括设计中各种不同类型晶体管的规则定义。 第一部分生成用于输入到电路仿真器的打印文件。 第二部分读取打印文件，规则文件和模拟器输出文件。 第二部分产生链接到规则链表的晶体管链表。 第二部分逐行读取模拟器输出文件，并为每个时间步骤对每个晶体管执行高压电气规则检查。 第二部分为每个违规类型的每个晶体管产生违规链表。 只有表示违规序列的开始或结束的点将被添加到违例链接列表中。 第二部分保留对应于每个违规类型的变量，这些变量表示每个晶体管的最大违规量和时间。 第二部分产生每个晶体管违规的报告，并在每个晶体管完全检查后解除违规链表。 高电压规则检查程序使用动态链表数据结构来有效地最小化运行时的DRAM利用率。

公开(公告)号：US5973546A

公开(公告)日：1999-10-26

申请号：US93540

申请日：1998-06-08

申请人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer

发明人： Binh Quang Le ,  Pau-Ling Chen ,  Shane Hollmer

IPC分类号： G05F3/20 ,  H01L27/02 ,  H02M3/07 ,  G05F1/10

CPC分类号： H02M3/073 ,  G05F3/205 ,  H01L27/0222

摘要： A charge pump circuit having a fast rise time and reduced physical area is disclosed. The charge pump includes a plurality of stages having a non-uniform series of bootstrap capacitors. By using non-uniform capacitors at the various stages, charging rise time is enhanced while at the same time reducing the overall physical size of the charge pump.

摘要翻译： 公开了具有快速上升时间和减小的物理面积的电荷泵电路。 电荷泵包括具有不均匀系列的自举电容器的多个级。 通过在各个阶段使用不均匀的电容器，增加充电上升时间，同时降低电荷泵的整体物理尺寸。