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73 条记录 (耗时 0.023 秒)

    Interconnect-embedded metal-insulator-metal capacitor
    1.
    发明授权
    Interconnect-embedded metal-insulator-metal capacitor 有权
    互连嵌入式金属 - 绝缘体 - 金属电容器

    公开(公告)号：US06504202B1

    公开(公告)日：2003-01-07

    申请号：US09496971

    申请日：2000-02-02

    申请人： Derryl D. J. Allman ,  Kenneth Fuchs

    发明人： Derryl D. J. Allman ,  Kenneth Fuchs

    IPC分类号： H01L2976

    CPC分类号： H01L28/40 ,  H01L21/768 ,  H01L28/75

    摘要： A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

    摘要翻译： 金属 - 绝缘体 - 金属电容器嵌入在集成电路（IC）的互连层中。 互连层具有空腔，并且电容器形成在空腔中，电容器的一个板与互连层的导电层成一体，因此电容器板与互连层电连通。 互连层具有多个导电层，包括在制造IC期间在特定温度下经受变形的诸如铝的层，并且空腔延伸穿过该层。 互连层的剩余导电层限定电容器板中的一个，并且在腔内形成介电层和另一电容器板。 通过大致相同长度的互连电连接到顶板并且通过互连层连接到底板。

    Method of forming a metal-insulator-metal capacitor in an interconnect cavity
    2.
    发明授权
    Method of forming a metal-insulator-metal capacitor in an interconnect cavity 有权
    在互连腔中形成金属 - 绝缘体 - 金属电容器的方法

    公开(公告)号：US07118985B2

    公开(公告)日：2006-10-10

    申请号：US10260824

    申请日：2002-09-27

    申请人： Derryl D. J. Allman ,  Kenneth Fuchs

    发明人： Derryl D. J. Allman ,  Kenneth Fuchs

    IPC分类号： H01L21/768 ,  H01L21/8242

    CPC分类号： H01L28/40 ,  H01L21/768 ,  H01L28/75

    摘要： A metal-insulator-metal capacitor is embedded in an interconnect layer of an integrated circuit (IC). The interconnect layer has a cavity, and the capacitor is formed in the cavity with one of the plates of the capacitor integral with a conductive layer of the interconnect layer, so the capacitor plate electrically communicates with the interconnect layer. The interconnect layer has multiple conductive layers, including a layer, such as aluminum, that is subject to deformation at certain temperatures during fabrication of the IC, and the cavity extends through this layer. A remaining conductive layer of the interconnect layer defines one of the capacitor plates, and a dielectric layer and another capacitor plate are formed thereon within the cavity. Via interconnects of about the same length electrically connect to the top plate and through the interconnect layer to the bottom plate.

    摘要翻译： 金属 - 绝缘体 - 金属电容器嵌入在集成电路（IC）的互连层中。 互连层具有空腔，并且电容器形成在空腔中，电容器的一个板与互连层的导电层成一体，因此电容器板与互连层电连通。 互连层具有多个导电层，包括在制造IC期间在特定温度下经受变形的诸如铝的层，并且空腔延伸穿过该层。 互连层的剩余导电层限定电容器板中的一个，并且在腔内形成介电层和另一电容器板。 通过大致相同长度的互连电连接到顶板并且通过互连层连接到底板。

    Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure
    4.
    发明授权
    Process for forming a low k carbon-doped silicon oxide dielectric material on an integrated circuit structure 有权
    在集成电路结构上形成低k碳掺杂氧化硅介电材料的工艺

    公开(公告)号：US06583026B1

    公开(公告)日：2003-06-24

    申请号：US09872058

    申请日：2001-05-31

    申请人： Derryl D. J. Allman ,  Ponce Saopraseuth ,  Hemanshu D. Bhatt

    发明人： Derryl D. J. Allman ,  Ponce Saopraseuth ,  Hemanshu D. Bhatt

    IPC分类号： H01L2176

    CPC分类号： H01L21/02126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/0234 ,  H01L21/31633

    摘要： A process for forming a low k carbon-doped silicon oxide dielectric material (lkc-dsodm) on an integrated circuit structure is characterized by improved planarity and good gap fill in high aspect ratio regions of the integrated circuit structure, as well as improved film strength and adherence, and less byproducts trapped in the film. The process comprises: depositing a plurality of layers of lkc-dsodm on an integrated circuit structure in a reactor; and pausing after depositing each layer of lkc-dsodm and before depositing a further layer of lkc-dsodm. The process can further include first forming a base or barrier layer of a silicon-rich and nitrogen-rich dielectric material over the integrated circuit structure, plasma etching the upper surface of the barrier layer to facilitate adhesion of the subsequently deposited lkc-dsodm to the barrier layer, and then, before depositing the first layer of lkc-dsodm, cooling the etched barrier layer down to within 10° C. or less of the subsequent deposition temperature used for formation of the film of lkc-dsodm. In another aspect of the invention the pausing step further includes, before deposition of the next layer of lkc-dsodm, flowing a source of non-reactive gas over the surface of the newly deposited layer of lkc-dsodm to facilitate outgassing and removal of byproducts resulting from the preceding formation and deposition of lkc-dsodm.

    摘要翻译： 在集成电路结构上形成低k碳掺杂氧化硅电介质材料（lkc-dsodm）的方法的特征在于集成电路结构的高纵横比区域中的平坦度和良好的间隙填充，以及改进的膜强度 和坚持，更少的副产品被困在电影中。 该方法包括：在反应器中的集成电路结构上沉积多层lkc-dsodm; 并且在沉积每层lkc-dsodm之后并在沉积另外一层lkc-dsodm之前暂停。 该方法还可以包括首先在集成电路结构上形成富硅和富氮介电材料的基底或阻挡层，等离子体蚀刻阻挡层的上表面，以便于随后沉积的lkc-dsodm粘附到 然后在沉积第一层lkc-dsodm之前，将蚀刻的阻挡层冷却到用于形成lkc-dsodm膜的后续沉积温度的10℃以内。 在本发明的另一方面，暂停步骤还包括在沉积下一层lkc-dsodm之前，将非反应性气体源流过新沉积的lkc-dsodm层的表面以便于除气和除去副产物 由于以前的lkc-dsodm的形成和沉积而产生。

    Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same
    7.
    发明授权
    Semiconductor wafer having a layer-to-layer alignment mark and method for fabricating the same 有权
    具有层间对准标记的半导体晶片及其制造方法

    公开(公告)号：US6136662A

    公开(公告)日：2000-10-24

    申请号：US311253

    申请日：1999-05-13

    申请人： Derryl D. J. Allman ,  Curtis C. Hainds ,  Charles W. Jurgensen ,  Brian R. Lee

    发明人： Derryl D. J. Allman ,  Curtis C. Hainds ,  Charles W. Jurgensen ,  Brian R. Lee

    IPC分类号： G03F9/00 ,  H01L23/544 ,  H01L21/76 ,  H01L21/302 ,  H01L21/4763

    CPC分类号： G03F9/708 ,  G03F9/7084 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

    摘要： A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.

    摘要翻译： 在半导体晶片中形成层间对准标记的方法包括在与半导体晶片相关联的衬底上沉积第一导体层的步骤。 该方法还包括在第一导体层中制造多个对准沟槽的步骤。 此外，该方法包括在第一导体层上沉积第一绝缘体层以填充对准沟槽的数量的步骤。 此外，该方法包括以下步骤：从对准沟槽的数量去除与第一绝缘体层相关联的材料，使得第一导体层的上表面和第一绝缘体层的上表面限定第一对准步骤特征，其具有 一个预定的高度。 该方法还包括在去除步骤之后在半导体晶片上沉积第二导体层的步骤。 还公开了半导体晶片。

    Method for forming a bipolar emitter using doped SOG
    8.
    发明授权
    Method for forming a bipolar emitter using doped SOG 失效
    使用掺杂SOG形成双极型发射极的方法

    公开(公告)号：US5322805A

    公开(公告)日：1994-06-21

    申请号：US961973

    申请日：1992-10-16

    申请人： Derryl D. J. Allman ,  Gayle W. Miller

    发明人： Derryl D. J. Allman ,  Gayle W. Miller

    IPC分类号： H01L27/06 ,  H01L21/225 ,  H01L21/331 ,  H01L21/8249 ,  H01L29/08 ,  H01L29/73 ,  H01L29/732

    CPC分类号： H01L29/66272 ,  H01L21/2255 ,  H01L29/0804

    摘要： A method for forming a bipolar emitter using doped SOG which employs diffusion instead of implanting, and which produces a shallow, low-resistance emitter using a variety of dopants besides boron and phosphorus. A layer of doped SOG is spun over a predefined base region. Portions of the SOG layer are defined for removal and removed, leaving the collector and emitter contact areas exposed. The SOG layer is densified and the dopants are driven into the base to form the emitter.

    摘要翻译： 使用掺杂SOG形成双极型发射体的方法，其使用扩散而不是植入，并且使用除硼和磷之外的各种掺杂剂产生浅的低电阻发射体。 在预定义的碱性区域上旋转一层掺杂的SOG。 SOG层的部分被限定为去除和去除，使集电极和发射极接触区域暴露。 SOG层被致密化并且掺杂剂被驱动到基底中以形成发射极。

    Coating solution for forming glassy layers
    9.
    发明授权
    Coating solution for forming glassy layers 失效
    用于形成玻璃层的涂层溶液

    公开(公告)号：US5302198A

    公开(公告)日：1994-04-12

    申请号：US582570

    申请日：1990-09-14

    申请人： Derryl D. J. Allman

    发明人： Derryl D. J. Allman

    IPC分类号： G03F1/08 ,  G03F7/09 ,  H01L21/027 ,  H01L23/532 ,  C09K3/00 ,  C08G77/00

    CPC分类号： H01L23/5329 ,  G03F7/091 ,  G03F7/094 ,  H01L21/0276 ,  H01L2924/0002

    摘要： There is disclosed a method for producing a spin-on glass composition with a high carbon content for use as coating layers on substrates such as semiconductor silicon wafers. Also provided are spin-on glass compositions with polyorganosiloxanes having at least 30 wt.% carbon. These spin-on glass compositions show improved resistance to O.sub.2 concentration variations during etching and have an extended shelf-life of more than one year. Methods of using these spin-on glass compositions and semiconductor products produced therefrom are also provided.

    摘要翻译： 公开了一种用于生产具有高碳含量的旋涂玻璃组合物的方法，用作诸如半导体硅晶片的基底上的涂层。 还提供了具有至少30重量％碳的聚有机硅氧烷的旋涂玻璃组合物。 这些旋涂玻璃组合物在蚀刻期间显示出改善的耐O2浓度变化的耐受性，并且具有超过一年的延长的保存期限。 还提供了使用这些旋涂玻璃组合物和由其制备的半导体产品的方法。

    Nanotube fuse structure
    10.
    发明授权
    Nanotube fuse structure 有权
    纳米管保险丝结构

    公开(公告)号：US07598127B2

    公开(公告)日：2009-10-06

    申请号：US11284503

    申请日：2005-11-22

    申请人： Bruce J. Whitefield ,  Derryl D. J. Allman ,  Thomas Rueckes ,  Claude L. Bertin

    发明人： Bruce J. Whitefield ,  Derryl D. J. Allman ,  Thomas Rueckes ,  Claude L. Bertin

    IPC分类号： H01L21/86

    CPC分类号： H01L23/5258 ,  H01L23/5256 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

    摘要： A method of forming a carbon nanotube fuse by depositing a carbon nanotube layer, then depositing a cap layer directly over the carbon nanotube layer. The cap layer is formed of a material that has an insufficient amount of oxygen to significantly oxidize the carbon nanotube layer under operating conditions, and is otherwise sufficiently robust to protect the carbon nanotube layer from oxygen and plasmas. A photoresist layer is formed over the cap layer, and the photoresist layer is patterned to define a desired size of fuse. Both the cap layer and the carbon nanotube layer are completely etched, without removing the photoresist layer, to define the fuse having two ends in the carbon nanotube layer. Just the cap layer is etched, without removing the photoresist layer, so as to reduce the cap layer by a desired amount at the edges of the cap layer under the photoresist layer, without damaging the carbon nanotube layer. The photoresist layer is removed, and electrically conductive contacts are formed on each of the two ends of the fuse.

    摘要翻译： 通过沉积碳纳米管层形成碳纳米管熔丝，然后在碳纳米管层上直接沉积覆盖层的方法。 盖层由具有不足量的氧的材料形成，以在操作条件下显着地氧化碳纳米管层，否则足够坚固以保护碳纳米管层免受氧气和等离子体的影响。 在盖层上形成光致抗蚀剂层，并且将光致抗蚀剂层图案化以限定所需尺寸的熔丝。 完全蚀刻盖层和碳纳米管层，而不去除光致抗蚀剂层，以限定在碳纳米管层中具有两端的熔丝。 只是盖层被蚀刻，而不去除光致抗蚀剂层，以便在光致抗蚀剂层下的盖层的边缘处将盖层减少所需量，而不损害碳纳米管层。 去除光致抗蚀剂层，并且在熔丝的两端的每一端上形成导电触点。