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    HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS
    1.
    发明申请
    HETERO-INTEGRATED STRAINED SILICON n- AND p- MOSFETS 有权
    HETERO-INTEGRATED应变硅n-和p- MOSFET

    公开(公告)号：US20070278517A1

    公开(公告)日：2007-12-06

    申请号：US11840029

    申请日：2007-08-16

    申请人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

    发明人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

    IPC分类号： H01L35/26 ,  H01L21/20

    CPC分类号： H01L29/1054 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/7842 ,  Y10S438/938

    摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

    摘要翻译： 本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。 以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。 通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。 然后在含有受损区域的含Si衬底上形成应变SiGe合金。 然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。 接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

    Hetero-integrated strained silicon n-and p-MOSFETs
    2.
    发明申请
    Hetero-integrated strained silicon n-and p-MOSFETs 有权
    异质集成应变硅n型和p型MOSFET

    公开(公告)号：US20060091377A1

    公开(公告)日：2006-05-04

    申请号：US10978715

    申请日：2004-11-01

    申请人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

    发明人： Diane Boyd ,  Juan Cai ,  Kevin Chan ,  Patricia Mooney ,  Kern Rim

    IPC分类号： H01L29/06

    CPC分类号： H01L29/1054 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L29/7842 ,  Y10S438/938

    摘要： The present invention provides semiconductor structures and a method of fabricating such structures for application of MOSFET devices. The semiconductor structures are fabricated in such a way so that the layer structure in the regions of the wafer where n-MOSFETs are fabricated is different from the layer structure in regions of the wafers where p-MOSFETs are fabricated. The structures are fabricated by first forming a damaged region with a surface of a Si-containing substrate by ion implanting of a light atom such as He. A strained SiGe alloy is then formed on the Si-containing substrate containing the damaged region. An annealing step is then employed to cause substantial relaxation of the strained SiGe alloy via a defect initiated strain relaxation. Next, a strained semiconductor cap such as strained Si is formed on the relaxed SiGe alloy.

    摘要翻译： 本发明提供半导体结构和制造用于施加MOSFET器件的这种结构的方法。 以这样的方式制造半导体结构，使得制造n-MOSFET的晶片区域中的层结构不同于制造p-MOSFET的晶片的区域中的层结构。 通过首先通过离子注入诸如He的光原子形成具有含Si衬底的表面的损伤区域来制造结构。 然后在含有受损区域的含Si衬底上形成应变SiGe合金。 然后采用退火步骤通过缺陷引发的应变弛豫引起应变SiGe合金的显着松弛。 接下来，在弛豫的SiGe合金上形成诸如应变Si的应变半导体盖。

    SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer
    5.
    发明申请
    SOI wafers with 30-100 A buried oxide (BOX) created by wafer bonding using 30-100 A thin oxide as bonding layer 有权
    具有30-100A掩埋氧化物（BOX）的SOI晶片，通过使用30-100A薄氧化物作为结合层的晶片接合产生

    公开(公告)号：US20050042841A1

    公开(公告)日：2005-02-24

    申请号：US10957833

    申请日：2004-10-04

    申请人： Diane Boyd ,  Hussein Hanafi ,  Erin Jones ,  Dominic Schepis ,  Leathen Shi

    发明人： Diane Boyd ,  Hussein Hanafi ,  Erin Jones ,  Dominic Schepis ,  Leathen Shi

    IPC分类号： H01L21/762 ,  H01L21/76 ,  H01L21/30 ,  H01L21/46

    CPC分类号： H01L21/76251 ,  H01L21/76243

    摘要： A method of fabricating a SOI wafer having a gate-quality, thin buried oxide region is provided. The wafer is fabricating by forming a substantially uniform thermal oxide on a surface of a Si-containing layer of a SOI substrate which includes a buried oxide region positioned between the Si-containing layer and a Si-containing substrate layer. Next, a cleaning process is employed to form a hydrophilic surface on the thermal oxide. A carrier wafer having a hydrophilic surface is provided and positioned near the substrate such that the hydrophilic surfaces adjoin each other. Room temperature bonding is then employed to bond the carrier wafer to the substrate. An annealing step is performed and thereafter, the Si-containing substrate of the silicon-on-insulator substrate and the buried oxide region are selectively removed to expose the Si-containing layer.

    摘要翻译： 提供一种制造具有栅极质量薄的掩埋氧化物区域的SOI晶片的方法。 通过在SOI衬底的含Si层的表面上形成基本上均匀的热氧化物来制造晶片，该衬底包括位于含Si层和含Si衬底层之间的掩埋氧化物区域。 接下来，使用清洁方法在热氧化物上形成亲水性表面。 提供具有亲水表面的载体晶片并且将其定位在基板附近，使得亲水表面彼此相邻。 然后使用室温粘合将载体晶片粘合到基底上。 进行退火工序，然后选择性地除去绝缘体上硅衬底的含硅衬底和掩埋氧化物区域以暴露含Si层。

    CMOS transistor structure including film having reduced stress by exposure to atomic oxygen
    6.
    发明申请
    CMOS transistor structure including film having reduced stress by exposure to atomic oxygen 失效
    CMOS晶体管结构包括通过暴露于原子氧而具有减小的应力的膜

    公开(公告)号：US20060131659A1

    公开(公告)日：2006-06-22

    申请号：US11318844

    申请日：2005-12-27

    申请人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

    发明人： Michael Belyansky ,  Diane Boyd ,  Bruce Doris ,  Oleg Gluschenkov

    IPC分类号： H01L29/94

    CPC分类号： H01L29/7843 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203

    摘要： A structure and method are provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A structure and method are further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.

    摘要翻译： 提供了一种结构和方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。 在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。 还提供了一种结构和方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。 然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率 另一个是NFET和PFET。

    Hybrid planar and FinFET CMOS devices
    7.
    发明申请
    Hybrid planar and FinFET CMOS devices 有权
    混合平面和FinFET CMOS器件

    公开(公告)号：US20050263831A1

    公开(公告)日：2005-12-01

    申请号：US11122193

    申请日：2005-05-04

    申请人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

    发明人： Bruce Doris ,  Diane Boyd ,  Meikei Ieong ,  Thomas Kanarsky ,  Jakub Kedzierski ,  Min Yang

    IPC分类号： H01L29/423 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/49 ,  H01L29/786 ,  H01L31/113

    CPC分类号： H01L27/1211 ,  H01L21/845 ,  H01L29/66795 ,  H01L29/785

    摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.

    摘要翻译： 本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。 具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上， 绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。 还提供了一种形成集成电路的方法。 在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。 经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

    ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE
    8.
    发明申请
    ULTRA-THIN Si MOSFET DEVICE STRUCTURE AND METHOD OF MANUFACTURE 审中-公开
    超薄SiFET器件结构及其制造方法

    公开(公告)号：US20070228473A1

    公开(公告)日：2007-10-04

    申请号：US11758265

    申请日：2007-06-05

    申请人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

    发明人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

    IPC分类号： H01L29/786

    CPC分类号： H01L21/26533 ,  H01L21/2658 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/1083 ,  H01L29/49 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/78

    摘要： The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.

    摘要翻译： 本发明包括用于形成超薄沟道MOSFET的方法和由其制造的超薄沟道MOSFET。 具体地说，该方法包括：在SOI层的下方提供具有掩埋绝缘层的SOI衬底; 在SOI层顶上形成焊盘堆叠; 通过所述垫堆叠的顶部形成具有通道的块掩模; 在所述掩埋绝缘层的顶部上的所述SOI层中提供局部氧化物区域，从而使所述SOI层的一部分变薄，所述局部氧化物区域与所述沟道通孔自对准; 在通道通道中形成一个门; 至少去除阻挡掩模; 以及在与SOI层的薄化部分邻接的SOI层中形成源极/漏极延伸部。 提供局部氧化物区域还包括通过沟道通孔将氧掺杂剂注入到SOI层的一部分中; 并退火掺杂剂以产生局部氧化物区域。

    Ultrathin-body schottky contact MOSFET
    9.
    发明申请
    Ultrathin-body schottky contact MOSFET 审中-公开
    超薄体肖特基接触MOSFET

    公开(公告)号：US20070001223A1

    公开(公告)日：2007-01-04

    申请号：US11172711

    申请日：2005-07-01

    申请人： Diane Boyd ,  Meikei Leong ,  Jakub Kedzierski ,  Ghavam Shahidi

    发明人： Diane Boyd ,  Meikei Leong ,  Jakub Kedzierski ,  Ghavam Shahidi

    IPC分类号： H01L27/12

    CPC分类号： H01L29/66643 ,  H01L29/66772 ,  H01L29/78654

    摘要： An ultra thin SOI MOSFET device structure and method of fabrication is presented. The device has a terminal composed of silicide, which terminal is forming a Schottky contact with the channel. A plurality of impurities are segregated on the silicide/channel interface, and these segregated impurities determine the resistance of the Schottky contact. Such impurity segregation is achieved by a so called silicidation induced impurity segregation process. Silicon substitutional impurities are appropriate for accomplishing such a segregation.

    摘要翻译： 提出了一种超薄SOI MOSFET器件结构及其制造方法。 该器件具有由硅化物构成的端子，该端子与沟道形成肖特基接触。 多个杂质在硅化物/沟道界面上分离，这些分离的杂质决定了肖特基接触的电阻。 这种杂质偏析通过所谓的硅化物诱导的杂质分离过程来实现。 硅替代杂质适合于实现这种分离。

    Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
    10.
    发明申请
    Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique 有权
    超薄Si沟道MOSFET采用自对准氧注入和镶嵌技术

    公开(公告)号：US20050116289A1

    公开(公告)日：2005-06-02

    申请号：US10725849

    申请日：2003-12-02

    申请人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

    发明人： Diane Boyd ,  Bruce Doris ,  Meikei Ieong ,  Devendra Sadana

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L27/01

    CPC分类号： H01L29/78696 ,  H01L29/66545 ,  H01L29/66772 ,  H01L29/78609 ,  H01L29/78684

    摘要： The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.

    摘要翻译： 本发明提供一种具有低外部电阻的薄沟道MOSFET。 广义而言，包括位于掩埋绝缘层顶部的SOI层的绝缘体上硅结构，所述SOI层具有沟槽区，该沟道区被存在位于并接触之下的下面的局部氧化物区域而变薄 与所述掩埋绝缘层; 以及位于所述SOI层上方的栅极区域，其中所述局部氧化物区域与栅极区域自对准。 还提供了一种用于形成本发明的MOSFET的方法，包括在衬底顶部形成虚拟栅极区; 通过所述伪栅极注入形成氧化物的掺杂剂，以在与沟道区域的伪栅极区对准的衬底的一部分中产生局部氧化物区域; 形成邻接所述沟道区的源/漏扩展区; 并用栅极导体代替虚拟栅极。