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    Store-operate-coherence-on-value
    4.
    发明授权
    Store-operate-coherence-on-value 有权
    存储操作一致性值

    公开(公告)号：US08892824B2

    公开(公告)日：2014-11-18

    申请号：US12986652

    申请日：2011-01-07

    申请人： Dong Chen ,  Philip Heidelberger ,  Sameer Kumar ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    发明人： Dong Chen ,  Philip Heidelberger ,  Sameer Kumar ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    IPC分类号： G06F12/02 ,  G06F9/30 ,  G06F12/08 ,  G06F9/38

    CPC分类号： G06F12/0815 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  Y02D10/13

    摘要： A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

    摘要翻译： 一种用于在包括多个处理器和至少一个高速缓冲存储器设备的并行计算环境中执行各种存储操作指令的系统，方法和计算机程序产品。 系统中的队列从处理器接收存储操作指令，该指令指定在哪个条件下调用高速缓存一致性操作。 系统中的硬件单元运行接收到的存储操作指令。 硬件单元评估运行接收到的存储操作指令的结果是否满足条件。 如果结果满足条件，则硬件单元调用与接收到的存储操作指令相关联的高速缓存存储器地址的高速缓存一致性操作。 否则，硬件单元不会调用高速缓存存储器设备上的高速缓存一致性操作。

    STORE-OPERATE-COHERENCE-ON-VALUE
    6.
    发明申请
    STORE-OPERATE-COHERENCE-ON-VALUE 有权
    存储操作相关值

    公开(公告)号：US20110179229A1

    公开(公告)日：2011-07-21

    申请号：US12986652

    申请日：2011-01-07

    申请人： Dong Chen ,  Philip Heidelberger ,  Sameer Kumar ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    发明人： Dong Chen ,  Philip Heidelberger ,  Sameer Kumar ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0815 ,  G06F9/30043 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/3834 ,  Y02D10/13

    摘要： A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

    摘要翻译： 一种用于在包括多个处理器和至少一个高速缓冲存储器设备的并行计算环境中执行各种存储操作指令的系统，方法和计算机程序产品。 系统中的队列从处理器接收存储操作指令，该指令指定在哪个条件下调用高速缓存一致性操作。 系统中的硬件单元运行接收到的存储操作指令。 硬件单元评估运行接收到的存储操作指令的结果是否满足条件。 如果结果满足条件，则硬件单元调用与接收到的存储操作指令相关联的高速缓存存储器地址的高速缓存一致性操作。 否则，硬件单元不会调用高速缓存存储器设备上的高速缓存一致性操作。

    LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION
    8.
    发明申请
    LOW LATENCY MEMORY ACCESS AND SYNCHRONIZATION 失效
    低延迟存储器访问和同步

    公开(公告)号：US20070204112A1

    公开(公告)日：2007-08-30

    申请号：US11617276

    申请日：2006-12-28

    申请人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    发明人： Matthias Blumrich ,  Dong Chen ,  Paul Coteus ,  Alan Gara ,  Mark Giampapa ,  Philip Heidelberger ,  Dirk Hoenicke ,  Martin Ohmacht ,  Burkhard Steinmacher-Burow ,  Todd Takken ,  Pavlos Vranas

    IPC分类号： G06F12/14

    CPC分类号： G06F12/0862 ,  G06F9/52 ,  G06F2212/6028

    摘要： A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed. A memory line is redefined so that in addition to the normal physical memory data, every line includes a pointer that is large enough to point to any other line in the memory, wherein the pointers to determine which memory line to prefetch rather than some other predictive algorithm. This enables hardware to effectively prefetch memory access patterns that are non-contiguous, but repetitive.

    摘要翻译： 与弱有序的多处理器系统相关联地提供低延迟存储器系统访问。 多处理器中的每个处理器共享资源，并且每个共享资源在锁定设备内具有关联的锁，其提供对多处理器中的多个处理器之间的同步的支持以及资源的有序共享。 当处理器拥有与该资源相关联的锁定时，处理器仅具有访问资源的权限，并且处理器拥有锁的尝试仅需要单个加载操作，而不是传统的原子负载后跟存储，使得处理器 只执行读取操作，并且硬件锁定装置执行后续的写入操作而不是处理器。 还公开了用于非连续数据结构的简单预取。 重新定义存储器线，使得除了正常的物理存储器数据之外，每行包括足够大的指针以指向存储器中的任何其他行，其中指针用于确定要预取的存储器行而不是一些其它预测 算法。 这使得硬件能够有效地预取不连续但重复的存储器访问模式。

    PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN
    9.
    发明申请
    PAUSE PROCESSOR HARDWARE THREAD UNTIL PIN 失效
    暂停处理器硬件螺纹密码

    公开(公告)号：US20110173422A1

    公开(公告)日：2011-07-14

    申请号：US12684860

    申请日：2010-01-08

    申请人： Dong Chen ,  Mark Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  David L. Satterfield ,  Burkhard Steinmacher-Burow ,  Krishnan Sugavanam

    发明人： Dong Chen ,  Mark Giampapa ,  Philip Heidelberger ,  Martin Ohmacht ,  David L. Satterfield ,  Burkhard Steinmacher-Burow ,  Krishnan Sugavanam

    IPC分类号： G06F9/44 ,  G06F15/00 ,  G06F9/06

    CPC分类号： G06F9/30079 ,  G06F9/3851

    摘要： A system and method for enhancing performance of a computer which includes a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program are executed by a processer. The processor processes instructions from the program. A wait state in the processor waits for receiving specified data. A thread in the processor has a pause state wherein the processor waits for specified data. A pin in the processor initiates a return to an active state from the pause state for the thread. A logic circuit is external to the processor, and the logic circuit is configured to detect a specified condition. The pin initiates a return to the active state of the thread when the specified condition is detected using the logic circuit.

    摘要翻译： 一种用于增强计算机性能的系统和方法，其包括包括数据存储装置的计算机系统。 计算机系统包括存储在数据存储装置中的程序，程序的步骤由处理器执行。 处理器处理来自程序的指令。 处理器中的等待状态等待接收指定的数据。 处理器中的线程具有暂停状态，其中处理器等待指定的数据。 处理器中的引脚从线程的暂停状态启动返回到活动状态。 逻辑电路在处理器外部，并且逻辑电路被配置为检测指定的条件。 当使用逻辑电路检测到指定的条件时，引脚启动返回到线程的活动状态。