公开(公告)号：US20070004226A1

公开(公告)日：2007-01-04

申请号：US11174350

申请日：2005-07-01

申请人： Douglas Tweet ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

发明人： Douglas Tweet ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

IPC分类号： H01L21/31

CPC分类号： H01L21/02192 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/3147

摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

摘要翻译： 一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

公开(公告)号：US20060189111A1

公开(公告)日：2006-08-24

申请号：US11060878

申请日：2005-02-18

申请人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Yoshi Ono ,  Sheng Hsu

发明人： Jong-Jan Lee ,  Jer-Shen Maa ,  Douglas Tweet ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L27/127 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/7842 ,  H01L29/78621

摘要： A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.

摘要翻译： 在玻璃上的应变硅上制造CMOS器件的方法包括制备玻璃衬底，包括在玻璃衬底上形成应变硅层; 通过应变硅层的等离子体氧化形成氧化硅层; 在氧化硅层上沉积掺杂多晶硅层; 形成多晶硅栅极; 注入离子以形成LDD结构; 在栅极结构上沉积和形成间隔电介质; 植入和激活离子以形成源和漏结构; 沉积一层金属膜; 退火金属膜层，在源极，漏极和栅极结构上形成硅化物; 去除任何未反应的金属膜; 沉积层间电介质层; 并形成接触孔和金属化。

公开(公告)号：US20060091554A1

公开(公告)日：2006-05-04

申请号：US11311546

申请日：2005-12-19

申请人： Wei Pan ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

发明人： Wei Pan ,  Yoshi Ono ,  David Evans ,  Sheng Hsu

IPC分类号： H01L23/48

CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

摘要翻译： 通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。 多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。 在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。 整个多层膜的厚度可以是大约50埃。 当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。 本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

公开(公告)号：US20070259127A1

公开(公告)日：2007-11-08

申请号：US11416986

申请日：2006-05-02

申请人： Yoshi Ono ,  Bruce Ulrich ,  Wei-Wei Zhuang ,  Douglas Tweet

发明人： Yoshi Ono ,  Bruce Ulrich ,  Wei-Wei Zhuang ,  Douglas Tweet

IPC分类号： B05D5/06 ,  B05D3/12 ,  B05D3/02 ,  H05H1/00

CPC分类号： G02B3/0012 ,  H01L27/14627

摘要： A method for densifying sol-gel films to form microlens structures includes preparing a sol-gel precursor, having at least one solvent therein. The sol-gel precursor is spin coated onto a wafer to form a sol-gel film thereon. The wafer and sol-gel film are hot plate baked at a temperature less than 200° C. to remove at least some of the solvent. The baked, wafer and spin-coated sol-gel film are treated with an oxygen plasma treatment to remove any remaining solvent and to densify the sol-gel film. The spin coating, hot plate baking and treating steps may be repeated as required. A microlens is formed from the densified sol-gel film.

摘要翻译： 用于致密化溶胶 - 凝胶膜以形成微透镜结构的方法包括制备其中具有至少一种溶剂的溶胶 - 凝胶前体。 将溶胶 - 凝胶前体旋涂在晶片上以在其上形成溶胶 - 凝胶膜。 将晶片和溶胶 - 凝胶膜在低于200℃的温度下进行热板烘烤以除去至少一些溶剂。 用氧等离子体处理烘烤，晶片和旋涂溶胶 - 凝胶膜以除去任何残留的溶剂并致密化溶胶 - 凝胶膜。 可以根据需要重复旋涂，热板烘烤和处理步骤。 从致密化的溶胶 - 凝胶膜形成微透镜。

公开(公告)号：US20060250072A1

公开(公告)日：2006-11-09

申请号：US11123603

申请日：2005-05-06

申请人： Sheng Hsu ,  Yoshi Ono

发明人： Sheng Hsu ,  Yoshi Ono

IPC分类号： H01J1/62 ,  H01J63/04

CPC分类号： H01L33/0004 ,  H01L33/26

摘要： A method is provided for forming a ZnO Si N—I—N EL device. The method comprises: forming an n-doped Si layer; forming a Si oxide (SiO2) layer overlying the n-doped Si layer; forming an n-type ZnO layer overlying the SiO2 layer; and, forming an electrode overlying the ZnO layer. The electrode can be a transparent material such as indium tin oxide, zinc oxyfluoride, or a conductive plastic. The n-doped Si layer can be polycrystalline or single-crystal Si. In some aspects, the Si oxide layer has a thickness in the range of 1 to 20 nm. More preferably, the thickness is 2 to 5 nm. The ZnO layer thickness is in the range of 10 to 200 nm.

公开(公告)号：US20060172555A1

公开(公告)日：2006-08-03

申请号：US11049594

申请日：2005-02-01

申请人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/31

CPC分类号： C23C14/5806 ,  C23C14/10

摘要： A method of forming a silicon-rich silicon oxide layer having nanometer sized silicon particles therein includes preparing a substrate; preparing a target; placing the substrate and the target in a sputtering chamber; setting the sputtering chamber parameters; depositing material from the target onto the substrate to form a silicon-rich silicon oxide layer; and annealing the substrate to form nanometer sized silicon particles therein.

摘要翻译： 形成其中具有纳米尺寸硅颗粒的富硅氧化硅层的方法包括制备衬底; 准备一个目标 将基板和靶放置在溅射室中; 设置溅射室参数; 将材料从靶材沉积到衬底上以形成富硅氧化硅层; 并对衬底退火以在其中形成纳米尺寸的硅颗粒。

公开(公告)号：US20060180816A1

公开(公告)日：2006-08-17

申请号：US11058505

申请日：2005-02-14

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L29/26

CPC分类号： H05B33/145

摘要： A method is provided for forming a Si electroluminescence (EL) device for emitting light at short wavelengths. The method comprises: providing a substrate; forming a first insulator layer overlying the substrate; forming a silicon-rich silicon oxide (SRSO) layer overlying the first insulator layer, embedded with nanocrystalline Si having a size in the range of 0.5 to 5 nm; forming a second insulator layer overlying the SRSO layer; and, forming a top electrode. Typically, the SRSO has a Si richness in the range of 5 to 40%. In one aspect, the SRSO layer is formed using a DC sputtering process. In another aspect, the SRSO formation step includes a rapid thermal annealing (RTA) process subsequent to depositing the SRSO. Likewise, thermal oxidation or plasma oxidation can be performed subsequent to the SRSO layer deposition. The size of Si nanocrystals is decreased in response to above-mentioned deposition, annealing, and oxidation processes.

摘要翻译： 提供一种用于形成用于发射短波长的光的Si电致发光（EL）装置的方法。 该方法包括：提供衬底; 形成覆盖所述衬底的第一绝缘体层; 形成覆盖在第一绝缘体层上的富硅氧化物（SRSO）层，其中嵌入尺寸在0.5至5nm范围内的纳米晶体Si; 形成覆盖所述SRSO层的第二绝缘体层; 并形成顶部电极。 通常，SRSO的Si浓度范围为5〜40％。 在一个方面，使用DC溅射工艺形成SRSO层。 另一方面，SRSO形成步骤包括在沉积SRSO之后的快速热退火（RTA）工艺。 同样地，可以在SRSO层沉积之后进行热氧化或等离子体氧化。 响应于上述沉积，退火和氧化过程，Si纳米晶体的尺寸减小。

公开(公告)号：US20060160335A1

公开(公告)日：2006-07-20

申请号：US11039463

申请日：2005-01-19

申请人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

发明人： Tingkai Li ,  Wei Gao ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L21/20

CPC分类号： C23C14/16 ,  C03C17/34 ,  C23C14/10 ,  C23C28/322 ,  C23C28/323 ,  C23C28/345 ,  C23C28/3455 ,  C23C28/42 ,  H01L21/02164 ,  H01L21/02266 ,  H01L21/0237 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/0259 ,  H01L21/02631 ,  H01L21/02667 ,  H01L21/31608 ,  H01L33/26

摘要： Provided are an electroluminescence (EL) device and corresponding method for forming a rare earth element-doped silicon (Si)/Si dioxide (SiO2) lattice structure. The method comprises: providing a substrate; DC sputtering a layer of amorphous Si overlying the substrate; DC sputtering a rare earth element; in response, doping the Si layer with the rare earth element; DC sputtering a layer of SiO2 overlying the rare earth-doped Si; forming a lattice structure; annealing; and, in response to the annealing, forming nanocrystals in the rare-earth doped Si having a grain size in the range of 1 to 5 nanometers (nm). In one aspect, the rare earth element and Si are co-DC sputtered. Typically, the steps of DC sputtering Si, DC sputtering the rare earth element, and DC sputtering the SiO2 are repeated 5 to 60 cycles, so that the lattice structure includes the plurality (5-60) of alternating SiO2 and rare earth element-doped Si layers.

摘要翻译： 提供了一种用于形成稀土元素掺杂硅（Si）/二氧化硅（SiO 2）晶格结构的电致发光（EL）器件和相应的方法。 该方法包括：提供衬底; DC溅射覆盖衬底的非晶硅层; 直流溅射稀土元素; 作为响应，用稀土元素掺杂Si层; DC溅射一层SiO 2，覆盖稀土掺杂的Si; 形成晶格结构; 退火; 并且响应于退火，在具有1至5纳米（nm）范围内的晶粒尺寸的稀土掺杂Si中形成纳米晶体。 一方面，稀土元素和Si共溅射。 通常，DC溅射Si，DC溅射稀土元素和DC溅射SiO 2的步骤重复5至60个循环，使得晶格结构包括多个（5-60）交替的SiO 2和稀土元素掺杂 Si层。

公开(公告)号：US20050088898A1

公开(公告)日：2005-04-28

申请号：US10976596

申请日：2004-10-29

申请人： Sheng Hsu ,  Yoshi Ono

发明人： Sheng Hsu ,  Yoshi Ono

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00

CPC分类号： H01L21/28194 ,  H01L21/76224 ,  H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/7883 ,  Y10S438/975

摘要： Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.

摘要翻译： 闪存单元设置有插入在浮置多晶硅栅极和控制栅极之间的高k材料。 在浮置多晶硅栅极和衬底之间插入隧道氧化物。 还提供了形成闪存单元的方法，包括在衬底上形成第一多晶硅层。 通过第一多晶硅层形成沟槽并进入衬底，并用氧化物层填充沟槽。 在氧化物上沉积第二多晶硅层，使得沟槽内的第二多晶硅层的底部高于第一多晶硅层的底部，并且沟槽内的第二多晶硅层的顶部低于第一多晶硅的顶部 层。 然后可以使用CMP工艺将得到的结构平坦化。 然后可以在第一多晶硅层上沉积高k电介质层。 然后可以在高k电介质层上沉积第三多晶硅层，并使用光致抗蚀剂图案化以形成闪存栅极结构。 在图案化期间，蚀刻暴露的第二多晶硅层。 在完成去除第二多晶硅层时检测到蚀刻停止。 保留第一多晶硅层的薄层，使用随后的选择性蚀刻工艺小心地去除。 结合形成闪速存储器单元的过程，高k电介质层可以被图案化以允许形成非存储晶体管。

公开(公告)号：US20080035946A1

公开(公告)日：2008-02-14

申请号：US11973525

申请日：2007-10-09

申请人： Wei Gao ,  Tingkai Li ,  Robert Barrowcliff ,  Yoshi Ono ,  Sheng Hsu

发明人： Wei Gao ,  Tingkai Li ,  Robert Barrowcliff ,  Yoshi Ono ,  Sheng Hsu

IPC分类号： H01L33/00 ,  H01L23/58

CPC分类号： H05B33/145 ,  H01L21/3115 ,  H01L31/03046 ,  Y02E10/544

摘要： A method is provided for forming a rare earth (RE) element-doped silicon (Si) oxide film with nanocrystalline (nc) Si particles. The method comprises: providing a first target of Si, embedded with a first rare earth element; providing a second target of Si; co-sputtering the first and second targets; forming a Si-rich Si oxide (SRSO) film on a substrate, doped with the first rare earth element; and, annealing the rare earth element-doped SRSO film. The first target is doped with a rare earth element such as erbium (Er), ytterbium (Yb), cerium (Ce), praseodymium (Pr), or terbium (Tb). The sputtering power is in the range of about 75 to 300 watts (W). Different sputtering powers are applied to the two targets. Also, deposition can be controlled by varying the effective areas of the two targets. For example, one of the targets can be partially covered.

摘要翻译： 提供了一种用于形成具有纳米晶体（nc）Si颗粒的稀土（RE）元素掺杂硅（Si）氧化物膜的方法。 该方法包括：提供嵌入有第一稀土元素的Si的第一靶; 提供Si的第二个目标; 共溅射第一和第二个目标; 在掺杂有第一稀土元素的衬底上形成富Si氧化硅（SRSO）膜; 并对稀土元素掺杂的SRSO膜退火。 第一靶用铒（Er），镱（Yb），铈（Ce），镨（Pr）或铽（Tb）等稀土元素掺杂。 溅射功率在约75至300瓦（W）的范围内。 不同的溅射功率被应用于两个目标。 此外，可以通过改变两个目标的有效面积来控制沉积。 例如，其中一个目标可以被部分覆盖。