公开(公告)号：US5252506A

公开(公告)日：1993-10-12

申请号：US879697

申请日：1992-05-05

申请人： Duane E. Carter ,  William R. McKee ,  Gishi Chung ,  Fred D. Fishburn

发明人： Duane E. Carter ,  William R. McKee ,  Gishi Chung ,  Fred D. Fishburn

IPC分类号： H01L21/8242 ,  H01L21/306

CPC分类号： H01L27/10861

摘要： A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.

摘要翻译： 公开了一种用于防止在诸如使用场板隔离的VLSI动态随机存取存储器的集成电路器件中形成不需要的多晶硅字线栅极细丝的方法。 在处理字线之前，沿着场板开口的边缘在氮化物侧壁下方的场板开口中形成氧化物层。 氧化物层部分地填充氮化物侧壁下方的浸渍下方的底切区域。 去除氮化物侧壁的浸出。 脱落区域的去除以及部分填充底切区域减少了当字线稍后添加时，多晶硅字线细丝在底切区域的场板开口的边缘周围形成的可能性。 还公开了一种场板隔离存储器件，其中沿着场板开口的边缘，部分填充的氧化物层和侧壁氮化物层几乎重合。

公开(公告)号：US5352913A

公开(公告)日：1994-10-04

申请号：US204909

申请日：1994-03-02

申请人： Gishi Chung ,  William R. McKee ,  Clarence W. Teng

发明人： Gishi Chung ,  William R. McKee ,  Clarence W. Teng

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/68 ,  H01L29/92

CPC分类号： H01L27/10861 ,  H01L28/40

摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.

摘要翻译： 公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。 沟槽蚀刻成半导体材料体的表面。 创建围绕沟槽的存储节点。 在沟槽壁上形成多晶硅层。 在与沟槽壁上的多晶硅层相邻的沟槽壁上形成存储电介质层，使得沟槽壁上的多晶硅层位于存储介电层和存储节点之间。 沟槽壁上的多晶硅层减少了来自存储节点的泄漏电流。 还公开了沟槽型场板隔离随机存取存储单元结构。

公开(公告)号：US5112762A

公开(公告)日：1992-05-12

申请号：US622468

申请日：1990-12-05

申请人： Dirk N. Anderson ,  William R. McKee ,  Gishi Chung

发明人： Dirk N. Anderson ,  William R. McKee ,  Gishi Chung

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/32 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L29/66181 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/26586 ,  H01L21/31662 ,  H01L21/32

摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.

摘要翻译： 公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。 电容器的存储节点通过将诸如注入的砷的存储节点材料以第一倾斜和第二倾斜放置在器件的沟槽壁中而形成。 第二倾斜的角度优选地比第一倾斜的角度更大，更高。 这种较高的角度为存储节点提供了围绕沟槽壁上部的更大的掺杂浓度。 这种较大的掺杂浓度降低了从存储节点的上部泄漏到半导体材料的衬底中的电荷。 还公开了一种用于动态随机存取存储器件的沟槽型存储电容器。

公开(公告)号：US5251168A

公开(公告)日：1993-10-05

申请号：US738383

申请日：1991-07-31

申请人： Gishi Chung ,  William R. McKee ,  William F. Richardson ,  Lionel S. White, Jr.

发明人： Gishi Chung ,  William R. McKee ,  William F. Richardson ,  Lionel S. White, Jr.

IPC分类号： H01L23/495 ,  H01L27/105 ,  H01L27/108 ,  G11C7/02

CPC分类号： H01L23/4951 ,  H01L27/10805 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/4826 ,  H01L24/48 ,  H01L27/105 ,  H01L2924/00014 ,  H01L2924/01014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041

摘要： By placing boundary cells within areas of discontinuity of a memory array, such as in word line strap areas, stress on edge cells of the memory array is reduced; the reduction of stress improves leakage characteristics and pause-refresh capabilities of edge cells. The boundary cells may further be laid out in the areas of discontinuity with the same pattern as the memory array. Some of the boundary cells may be electrically biased to act as minority carrier sinks. By collecting minority carriers that otherwise may be attracted to edge cells of the memory array, the leakage characteristics of the edge cells and their pause-refresh capabilities are further enhanced. The boundary cells are particularly useful in improving leakage characteristics of dynamic random access memory devices of the trench capacitor type.

摘要翻译： 通过将边界单元放置在存储器阵列的不连续区域内，例如在字线带区域中，存储器阵列的边缘单元上的应力减小; 压力的降低提高了边缘电池的泄漏特性和暂停刷新能力。 边界单元可以进一步布置在具有与存储器阵列相同的图案的不连续区域中。 一些边界单元可以被电偏置以用作少数载流子阱。 通过收集否则可能被吸引到存储器阵列的边缘单元的少数载流子，边缘单元的泄漏特性及其暂停刷新能力得到进一步提高。 边界电池特别适用于改善沟槽电容器型动态随机存取存储器件的泄漏特性。

公开(公告)号：US5202279A

公开(公告)日：1993-04-13

申请号：US622465

申请日：1990-12-05

申请人： Gishi Chung ,  William R. McKee ,  Clarence W. Teng

发明人： Gishi Chung ,  William R. McKee ,  Clarence W. Teng

IPC分类号： H01L27/10 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10861 ,  H01L28/40

摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.

摘要翻译： 公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。 沟槽蚀刻成半导体材料体的表面。 创建围绕沟槽的存储节点。 在沟槽壁上形成多晶硅层。 在与沟槽壁上的多晶硅层相邻的沟槽壁上形成存储电介质层，使得沟槽壁上的多晶硅层位于存储介电层和存储节点之间。 沟槽壁上的多晶硅层减少了来自存储节点的泄漏电流。 还公开了沟槽型场板隔离随机存取存储单元结构。

公开(公告)号：US07323727B2

公开(公告)日：2008-01-29

申请号：US11683930

申请日：2007-03-08

申请人： Goro Kitsukawa ,  Takesada Akiba ,  Hiroshi Otori ,  William R. McKee ,  Jeffrey E. Koelling ,  Troy H. Herndon

发明人： Goro Kitsukawa ,  Takesada Akiba ,  Hiroshi Otori ,  William R. McKee ,  Jeffrey E. Koelling ,  Troy H. Herndon

IPC分类号： H01L27/10

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

摘要翻译： 一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。 与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。 网格系统的功率和信号总线跨阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。 使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。 一旦连接，总线延伸到适当的感应放大器驱动器。 通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

公开(公告)号：US06831317B2

公开(公告)日：2004-12-14

申请号：US10315307

申请日：2002-12-10

申请人： Goro Kitsukawa ,  Takesada Akiba ,  Hiroshi Otori ,  William R. McKee ,  Jeffrey E. Koelling ,  Troy H. Herndon

发明人： Goro Kitsukawa ,  Takesada Akiba ,  Hiroshi Otori ,  William R. McKee ,  Jeffrey E. Koelling ,  Troy H. Herndon

IPC分类号： H01L31119

CPC分类号： G11C5/063 ,  G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C7/18 ,  G11C8/14 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10891 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

摘要翻译： 一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。 与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。 网格系统的功率和信号总线跨越阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。 使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。 一旦连接，总线延伸到适当的感应放大器驱动器。 通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

公开(公告)号：US06294420B1

公开(公告)日：2001-09-25

申请号：US09014724

申请日：1998-01-28

申请人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

发明人： Robert Tsu ,  Isamu Asano ,  Shinpei Iijima ,  William R. McKee

IPC分类号： H01L218242

CPC分类号： H01L28/75 ,  H01L21/28518 ,  H01L21/76897 ,  H01L28/55 ,  H01L28/90

摘要： The present invention discloses a novel integrated circuit capacitor and a method of forming such a capacitor. The capacitor formation begins with a base electrode 18 adjacent an insulating region 26. This base electrode 18 can comprise either polysilicon or a metal. A layer 28 of a first material, such as a siliciding metal, is formed over the base electrode 18 as well as the adjacent insulating region. A self-aligned capacitor electrode 12 can then be formed by reacting the first material 28 with the base electrode 18 and removing unreacted portions of the first material 28 from the insulating region 26. The capacitor is then completed by forming a dielectric layer 16 over the self-aligned capacitor electrode 12 and a second capacitor electrode 14 over the dielectric layer 16.

摘要翻译： 本发明公开了一种新颖的集成电路电容器及其形成方法。 电容器形成从邻近绝缘区域26的基极18开始。该基极18可以包括多晶硅或金属。 诸如硅化金属的第一材料的层28形成在基极电极18上以及相邻的绝缘区域上。 然后可以通过使第一材料28与基底电极18反应并从绝缘区域26去除第一材料28的未反应部分来形成自对准电容器电极12.然后通过在电容器电极12上形成介电层16来完成电容器 自对准电容器电极12和在电介质层16上的第二电容器电极14。

公开(公告)号：US06288925B1

公开(公告)日：2001-09-11

申请号：US09496079

申请日：2000-02-01

申请人： Goro Kitsukawa ,  Takesada Akiba ,  Hiroshi Otori ,  William R. McKee ,  Jeffrey E. Koelling ,  Troy H. Herndon

发明人： Goro Kitsukawa ,  Takesada Akiba ,  Hiroshi Otori ,  William R. McKee ,  Jeffrey E. Koelling ,  Troy H. Herndon

IPC分类号： G11C506

CPC分类号： G11C5/025 ,  G11C5/14 ,  G11C7/065 ,  G11C7/18 ,  G11C8/14

摘要： A method and apparatus for providing a meshed power and signal bus system on an array type integrated circuit that minimizes the size of the circuit. In a departure from the art, through-holes for the mesh system are placed in the cell array, as well as the peripheral circuits. The power and signal buses of the mesh system run in both vertical and horizontal directions across the array such that all the vertical buses lie in one metal layer, and all the horizontal buses lie in another metal layer. The buses of one layer are connected to the appropriate bus(es) of the other layer using through-holes located in the array. Once connected, the buses extend to the appropriate sense amplifier drivers. The method and apparatus are facilitated by an improved subdecoder circuit implementing a hierarchical word line structure.

摘要翻译： 一种用于在阵列型集成电路上提供网状电源和信号总线系统的方法和装置，其使电路的尺寸最小化。 与现有技术不同，用于网状系统的通孔被放置在电池阵列以及外围电路中。 网格系统的功率和信号总线跨越阵列在垂直和水平方向上运行，使得所有垂直总线位于一个金属层中，并且所有水平总线位于另一个金属层中。 使用位于阵列中的通孔将一层的总线连接到另一层的适当总线。 一旦连接，总线延伸到适当的感应放大器驱动器。 通过实现分级字线结构的改进的子解码器电路来促进该方法和装置。

公开(公告)号：US5216265A

公开(公告)日：1993-06-01

申请号：US809812

申请日：1991-12-18

申请人： Dirk N. Anderson ,  William R. McKee ,  Cishi Chung

发明人： Dirk N. Anderson ,  William R. McKee ,  Cishi Chung

IPC分类号： H01L21/265 ,  H01L21/316 ,  H01L21/32 ,  H01L21/334

CPC分类号： H01L29/66181 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02271 ,  H01L21/26586 ,  H01L21/31662 ,  H01L21/32

摘要： A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. The storage node of the capacitor is formed by placing a storage node material, such as implanted arsenic, into the trench walls of the device at a first tilt and a second tilt. The angle of the second tilt is preferably larger, higher, than the angle of the first tilt. This higher angle provides the storage node with a larger concentration of doping around the upper portion the trench walls. This larger concentration of doping reduces the charge leaking from the upper portion of the storage node into the substrate of semiconductor material. A trench type storage capacitor for a dynamic random access memory device is also disclosed.

摘要翻译： 公开了一种在沟槽电容器型场板隔离型动态随机存取存储器件中降低栅极二极管泄漏的方法。 电容器的存储节点通过将诸如注入的砷的存储节点材料以第一倾斜和第二倾斜放置在器件的沟槽壁中而形成。 第二倾斜的角度优选地比第一倾斜的角度更大，更高。 这种较高的角度为存储节点提供了围绕沟槽壁上部的更大的掺杂浓度。 这种较大的掺杂浓度降低了从存储节点的上部泄漏到半导体材料的衬底中的电荷。 还公开了一种用于动态随机存取存储器件的沟槽型存储电容器。