公开(公告)号：US09385056B2

公开(公告)日：2016-07-05

申请号：US13566323

申请日：2012-08-03

申请人： Dyi-Chung Hu ,  John Hon-Shing Lau

发明人： Dyi-Chung Hu ,  John Hon-Shing Lau

IPC分类号： H01L23/14 ,  H01L23/498 ,  H01L23/13

CPC分类号： H01L23/147 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  Y10T29/49165 ,  H01L2224/05599

摘要： A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

摘要翻译： 封装基板包括载体和插入件。 载体具有相对的顶部和底部表面。 在顶面形成有凹部，在凹部上形成有多个第一导电端子。 此外，在载体的底表面上形成多个第二导电端子。 插入器设置在凹部中并且具有相对的第一和第二表面以及穿过第一表面和第二表面的多个导电通孔。 第一导电焊盘形成在从第一表面暴露的每个导电通孔的端部上，并且第二导电焊盘形成在从第二表面暴露的每个导电通孔的另一端上并且电连接到 对应的第一导电端子之一。 与现有技术相比，本发明提高了产品的可靠性。

公开(公告)号：US20130032390A1

公开(公告)日：2013-02-07

申请号：US13566323

申请日：2012-08-03

申请人： Dyi-Chung Hu ,  John Hon-Shing Lau

发明人： Dyi-Chung Hu ,  John Hon-Shing Lau

IPC分类号： H05K1/11 ,  H05K3/42

CPC分类号： H01L23/147 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  Y10T29/49165 ,  H01L2224/05599

摘要： A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

摘要翻译： 封装基板包括载体和插入件。 载体具有相对的顶部和底部表面。 在顶面形成有凹部，在凹部上形成有多个第一导电端子。 此外，在载体的底表面上形成多个第二导电端子。 插入器设置在凹部中并且具有相对的第一和第二表面以及穿过第一表面和第二表面的多个导电通孔。 第一导电焊盘形成在从第一表面暴露的每个导电通孔的端部上，并且第二导电焊盘形成在从第二表面暴露的每个导电通孔的另一端上并且电连接到 对应的第一导电端子之一。 与现有技术相比，本发明提高了产品的可靠性。

公开(公告)号：US10964580B2

公开(公告)日：2021-03-30

申请号：US15374622

申请日：2016-12-09

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： B32B3/02 ,  B32B9/00 ,  H01L21/02 ,  H01L21/683 ,  B32B9/04 ,  B32B15/04 ,  B32B17/06 ,  B32B3/30 ,  B32B15/01 ,  B32B15/18 ,  B32B15/20 ,  G03F7/20 ,  H01L21/027 ,  H01L21/288

摘要： At least one wafer is embedded in a carrier to eliminate or at least reduce edge effect. The wafer reconfiguration is designed to improve a quality not only for spin coating process but also for electric plating process. An edge bead is formed on top of the carrier instead of being formed on top of the wafer so that a full top surface of the wafer can be active to the fabrication of chips and therefore more chips are yielded for a single wafer. The backside of the wafer is not contaminated by the coating according to the present invention. Further, dummy circuits can be made on top of the carrier so that electric plating uniformity for full area of a wafer can be improved.

公开(公告)号：US10395946B2

公开(公告)日：2019-08-27

申请号：US16177446

申请日：2018-11-01

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： H01L23/49 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L23/538 ,  H01L23/31

摘要： A method for manufacturing an electronic package includes: forming a middle patterned conductive layer having a first surface, a second surface opposite to the first surface, and a plurality of middle conductive pads; forming a first redistribution circuitry on the first surface, wherein the first redistribution circuitry includes a first patterned conductive layer having a plurality of first conductive elements, each first conductive element has a first conductive via and pad that form a T-shaped section, and each first conductive via connects the corresponding middle conductive pad and is tapering; and forming a second redistribution circuitry on the second surface, wherein the second redistribution circuitry includes a second patterned conductive layer having a plurality of second conductive elements, each second conductive element has a second conductive via and pad that form an inversed T-shaped section, and each second conductive via connects the corresponding middle conductive pad and is tapering.

公开(公告)号：US10304794B2

公开(公告)日：2019-05-28

申请号：US15694858

申请日：2017-09-04

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/78 ,  H01L23/28 ,  H05K1/11 ,  H01L21/683 ,  H01L23/31 ,  H01L21/56 ,  H01L25/065

摘要： A manufacturing method of an integrated circuit package including the following step is provided. A bottom redistribution layer according to IC design rule is fabricated. A top redistribution layer according to PCB design rule and using the first top pads as a starting point is fabricated. The bottom redistribution layer has a plurality of first bottom pads, a plurality of first top pads, at least one dielectric layer and a plurality of vias. Sides and the top of the bottom redistribution layer have interfaces with a lowermost dielectric layer of the top redistribution layer, a bottom surface of the lowermost dielectric layer opposite to the plurality of first top pads is coplanar with a bottom surface of the at least one dielectric layer opposite to the plurality of first top pads and surfaces of the plurality of first bottom pads exposed by the at least one dielectric layer.

公开(公告)号：US10049995B2

公开(公告)日：2018-08-14

申请号：US15708142

申请日：2017-09-19

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： H01L21/44 ,  H01L23/00 ,  H01L25/065

摘要： A bonding film has at least a left longitudinal branch, and a lower latitudinal branch; a first bonding area is configured in a first branch, and a second bonding area is configured in a second branch. A plurality of outer top metal pads and a plurality of inner top metal pads are exposed on a top surface within each bonding area. A central chip is configured in a central area of the bonding film and is electrically coupled to the inner top metal pad, and at least two peripheral chips are configured neighboring to the central chip and electrically coupled to the outer top metal pads. Each of the inner top metal pads is electrically coupled to a corresponding outer top metal pad through an embedded circuitry. The central chip communicates with the peripheral chips through the inner top metal pad, embedded circuitry, and outer top metal pad of the bonding film.

公开(公告)号：US10002852B1

公开(公告)日：2018-06-19

申请号：US15380716

申请日：2016-12-15

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： H01L21/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00

摘要： A first integrated circuit (IC) package has a package substrate on bottom. The package substrate comprises a bottom redistribution circuitry configured according to printed circuit board (PCB) design rule and a top redistribution circuitry configured according to integrated circuit (IC) design rule. The first IC package has a plurality of top metal pads and a plurality of copper pillars configured on a top side according to IC design rule. A second IC package has a plurality of bottom metal pads configured according to IC design rule configured on a top side of the first IC package. The first IC package electrically couples to the second IC package through the plurality of copper pillars.

公开(公告)号：US09691661B2

公开(公告)日：2017-06-27

申请号：US15073852

申请日：2016-03-18

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： H01L23/48 ,  H01L21/48 ,  H01L21/44 ,  H01L21/78 ,  H01L23/00 ,  H01L21/683

CPC分类号： H01L21/78 ,  H01L21/6835 ,  H01L24/03 ,  H01L24/06 ,  H01L2221/68318 ,  H01L2221/68345 ,  H01L2221/68359 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/06182

摘要： An IC package without using an interposer is disclosed to form a low profile IC package. A single redistribution layer is fabricated according to IC process. A plurality of bottom pads is formed on a bottom of the single redistribution layer adaptive for the IC package to mount onto a mother board. A plurality of top pads is formed on a top of the single redistribution layer. An IC chip mounts on the plurality of top pads. A first molding compound wraps the single redistribution layer on four sides; and a second molding compound embeds the IC chip on top of the redistribution layer.

公开(公告)号：US09545776B2

公开(公告)日：2017-01-17

申请号：US14604883

申请日：2015-01-26

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： B32B9/04 ,  B32B15/04 ,  B32B17/06 ,  G03F7/20

CPC分类号： H01L21/6835 ,  B32B3/02 ,  B32B3/30 ,  B32B9/00 ,  B32B9/04 ,  B32B15/012 ,  B32B15/018 ,  B32B15/04 ,  B32B15/18 ,  B32B15/20 ,  B32B17/06 ,  B32B17/061 ,  B32B2250/02 ,  B32B2255/00 ,  B32B2255/06 ,  B32B2255/26 ,  B32B2457/08 ,  B32B2457/14 ,  G03F7/2028 ,  H01L21/02282 ,  H01L21/0271 ,  H01L21/288 ,  H01L2224/27416

摘要： At least one water is embedded in a carrier to eliminate or at least reduce edge effect. The wafer reconfiguration is designed to improve a quality not only for spin coating process but also for electric plating process. An edge bead is formed on top of the carrier instead of being formed on top of the wafer so that a full top surface of the wafer can be active to the fabrication of chips and therefore more chips are yielded for a single wafer. The backside of the wafer is not contaminated by the coating according to the present invention. Further, dummy circuits can be made on top of the carrier so that electric plating uniformity for full area of a wafer can be improved.

摘要翻译： 至少一个水嵌入载体以消除或至少减少边缘效应。 晶圆重新配置旨在提高不仅用于旋涂工艺的质量，而且还可用于电镀工艺。 边缘焊道形成在载体的顶部上，而不是形成在晶片的顶部上，使得晶片的完整顶表面可以有助于制造芯片，因此为单个晶片产生更多的芯片。 晶片的背面不会被根据本发明的涂层污染。 此外，可以在载体的顶部上形成虚拟电路，从而可以提高晶片的整个面积的电镀均匀性。

公开(公告)号：US09543249B1

公开(公告)日：2017-01-10

申请号：US14859464

申请日：2015-09-21

申请人： Dyi-Chung Hu

发明人： Dyi-Chung Hu

IPC分类号： H01L23/34 ,  H01L23/538 ,  H01L25/065

CPC分类号： H01L23/5383 ,  H01L23/16 ,  H01L23/49816 ,  H01L23/5384 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/18161

摘要： A package substrate having a first redistribution layer (RDL1) and a second redistribution layer (RDL2) is disclosed for a multichip package. The first redistribution layer RDL1 is built according to a first design rule. The second redistribution layer RDL2 is built according to a second design rule and configured on a bottom of the first redistribution layer RDL1. The second design rule has a lower circuitry density than the first design rule has. A lateral communication circuitry is built within the first redistribution layer RDL1 according to the first design rule adaptive for bridging neighboring chips which are configured on a top surface of the first redistribution layer RDL1.

摘要翻译： 公开了一种具有第一再分布层（RDL1）和第二再分配层（RDL2）的封装衬底，用于多芯片封装。 第一个再分配层RDL1根据第一个设计规则构建。 第二再分发层RDL2根据第二设计规则构建并配置在第一再分发层RDL1的底部。 第二设计规则具有比第一设计规则更低的电路密度。 横向通信电路根据第一设计规则内置于第一重分配层RDL1内，该规则适用于桥接邻近的芯片，其配置在第一再分配层RDL1的顶表面上。