公开(公告)号：US20150091073A1

公开(公告)日：2015-04-02

申请号：US14229980

申请日：2014-03-30

申请人： EMEMORY TECHNOLOGY INC.

发明人： Yi-Hung Li ,  Yen-Hsin Lai ,  Ming-Shan Lo ,  Shih-Chan Huang

IPC分类号： H01L29/788

CPC分类号： G11C16/0433 ,  G11C16/0416 ,  G11C16/0441 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/3418 ,  G11C2216/10 ,  H01L27/11524 ,  H01L27/11558 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/42344 ,  H01L29/45 ,  H01L29/512 ,  H01L29/66545 ,  H01L29/66833 ,  H01L29/788 ,  H01L29/7881 ,  H01L29/7882 ,  H01L29/792

摘要： According to one embodiment, a single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is in direct contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

摘要翻译： 根据一个实施例，单多晶硅非易失性存储器（NVM）单元包括半导体衬底上的PMOS选择晶体管和连接到PMOS选择晶体管的PMOS浮栅晶体管串联。 PMOS浮栅晶体管包括在浮置栅极和半导体衬底之间的浮置栅极和栅氧化层。 保护层氧化物层覆盖并与浮动栅极直接接触。 接触蚀刻停止层设置在保护层氧化物层上，使得浮栅与保护层氧化物层与接触蚀刻停止层隔离。

公开(公告)号：US20190080778A1

公开(公告)日：2019-03-14

申请号：US16125779

申请日：2018-09-10

申请人： eMemory Technology Inc.

发明人： Kuan-Hsun Chen ,  Chun-Hung Lu ,  Ming-Shan Lo

IPC分类号： G11C17/18 ,  G11C17/16 ,  H01L27/112

摘要： A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.

公开(公告)号：US20180102376A1

公开(公告)日：2018-04-12

申请号：US15465616

申请日：2017-03-22

申请人： eMemory Technology Inc.

发明人： Yi-Hung Li ,  Ming-Shan Lo ,  Cheng-Da Huang

IPC分类号： H01L27/11524 ,  H01L23/528 ,  H01L29/06 ,  H01L23/31 ,  H01L29/49

CPC分类号： H01L27/11524 ,  G11C5/145 ,  G11C7/14 ,  G11C16/10 ,  G11C16/28 ,  G11C16/30 ,  G11C16/3459 ,  G11C29/021 ,  G11C29/028 ,  H01L23/3171 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/4916 ,  H01L29/4975

摘要： A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.

公开(公告)号：US10692981B2

公开(公告)日：2020-06-23

申请号：US16286609

申请日：2019-02-27

申请人： eMemory Technology Inc.

发明人： Yen-Ting Chen ,  Ming-Shan Lo

IPC分类号： H01L29/40 ,  G11C7/06 ,  G11C7/12 ,  G11C5/14 ,  G11C17/16 ,  G11C17/18 ,  H01L21/28 ,  H01L27/11517 ,  G11C7/08 ,  H01L21/02 ,  H01L29/06

摘要： A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.

公开(公告)号：US20180019250A1

公开(公告)日：2018-01-18

申请号：US15630927

申请日：2017-06-22

申请人： eMemory Technology Inc.

发明人： Ting-Ting Su ,  Kuan-Hsun Chen ,  Ming-Shan Lo

IPC分类号： H01L27/11524

CPC分类号： H01L27/11524 ,  G11C7/04 ,  G11C7/1084 ,  G11C7/109 ,  G11C16/0433 ,  G11C16/12 ,  H01L21/326 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11548 ,  H01L29/0646 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/7833 ,  H01L29/788 ,  H02M3/073 ,  H02M2001/007 ,  H05K999/99

摘要： A UV-erasable memory device with a UV transmitting window is disclosed. The UV-erasable memory device includes a substrate, two serially connected PMOS transistors on the substrate; an interlayer dielectric (ILD) layer covering the two PMOS transistors, a first intermetal dielectric (IMD) layer on the ILD layer, an intermediate layer on the first IMD layer, a UV transmitting window in the intermediate layer, and a second intermetal dielectric (IMD) layer on the first IMD layer and in the UV transmitting window.

公开(公告)号：US20190326304A1

公开(公告)日：2019-10-24

申请号：US16286609

申请日：2019-02-27

申请人： eMemory Technology Inc.

发明人： Yen-Ting Chen ,  Ming-Shan Lo

IPC分类号： H01L27/11517 ,  H01L21/28

摘要： A memory device and a manufacturing method thereof are provided. The memory device includes a first gate structure, a second gate structure, an oxide layer and a nitride layer. The first gate structure and the second gate structure are disposed on a substrate. The oxide layer covers the first gate structure. The nitride layer is disposed on the substrate and covers the oxide and the second gate structure. The refraction index of a portion of the nitride layer adjacent to an interface between the nitride layer and each of the first gate structure and the second gate structure is about 5% to 10% less than the refraction index of the remaining portion of the nitride layer.

公开(公告)号：US10083757B2

公开(公告)日：2018-09-25

申请号：US15293299

申请日：2016-10-14

申请人： eMemory Technology Inc.

发明人： Kuan-Hsun Chen ,  Ming-Shan Lo ,  Ting-Ting Su

IPC分类号： H01L27/115 ,  G11C16/14 ,  H01L29/423 ,  H01L29/45 ,  H01L29/78 ,  H01L29/788 ,  G11C16/04 ,  G11C16/10

CPC分类号： G11C16/14 ,  G11C16/0433 ,  G11C16/10 ,  H01L29/42328 ,  H01L29/452 ,  H01L29/7834 ,  H01L29/7881 ,  H01L29/7885

摘要： A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.

公开(公告)号：US20170110467A1

公开(公告)日：2017-04-20

申请号：US15293299

申请日：2016-10-14

申请人： eMemory Technology Inc.

发明人： Kuan-Hsun Chen ,  Ming-Shan Lo ,  Ting-Ting Su

IPC分类号： H01L27/115 ,  H01L29/78 ,  H01L29/45 ,  H01L29/788

CPC分类号： G11C16/14 ,  G11C16/0433 ,  G11C16/10 ,  H01L29/42328 ,  H01L29/452 ,  H01L29/7834 ,  H01L29/7881 ,  H01L29/7885

摘要： A single-poly NVM cell includes a select transistor and a floating gate transistor serially connected to the select transistor. The select transistor includes a select gate, a select gate oxide layer, a source doping region, a first LDD region merged with the source doping region, a commonly-shared doping region, and a second LDD region merged with the commonly-shared doping region. The floating gate transistor includes a floating gate, a floating gate oxide layer, the commonly-shared doping region, a third LDD region merged with the commonly-shared doping region, and a drain doping region. A drain-side extension modified region is disposed under the spacer and in proximity to the drain doping region.

公开(公告)号：US10664239B2

公开(公告)日：2020-05-26

申请号：US16125779

申请日：2018-09-10

申请人： eMemory Technology Inc.

发明人： Kuan-Hsun Chen ,  Chun-Hung Lu ,  Ming-Shan Lo

IPC分类号： G11C7/06 ,  G11C17/16 ,  G06F7/58 ,  H04L9/32 ,  G06F21/86 ,  H04L9/08 ,  G09C1/00 ,  H03K3/84 ,  G11C17/18 ,  H01L27/112 ,  H03K19/21

摘要： A method of programming a nonvolatile memory cell is provided according to an embodiment of the invention. The nonvolatile memory cell includes a substrate; and a select transistor, a following gate transistor, and an anti-fuse transistor comprising a first gate oxide layer, disposed on the substrate and coupled in series with each other. The programming method includes applying to said nonvolatile memory cell a variable DC voltage source comprising at least one high voltage part for forming a trapping path within the first gate oxide layer and at least one low voltage part for crystallizing the trapping path into a silicon filament.

公开(公告)号：US10283511B2

公开(公告)日：2019-05-07

申请号：US15465616

申请日：2017-03-22

申请人： eMemory Technology Inc.

发明人： Yi-Hung Li ,  Ming-Shan Lo ,  Cheng-Da Huang

IPC分类号： H01L27/11524 ,  H01L23/31 ,  H01L23/528 ,  H01L29/06 ,  H01L29/49 ,  G11C7/14 ,  G11C16/28 ,  G11C16/10 ,  G11C16/30 ,  G11C16/34 ,  G11C29/02 ,  G11C5/14

摘要： A non-volatile memory including memory cells is provided. Each of the memory cells includes a substrate, a floating gate structure, a select gate structure, and a first doped region. The floating gate structure is disposed on the substrate. The select gate structure is disposed on the substrate and located at one side of the floating gate structure. The first doped region is disposed in the substrate at another side of the floating gate structure. The first doped regions between two adjacent memory cells are adjacent to one another and separated from one another.