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公开(公告)号：US5767538A
公开(公告)日：1998-06-16
申请号：US728347
申请日：1996-10-09
IPC分类号： H03F1/08 , H03F3/08 , H01L29/74 , H01L27/148 , H01L29/768 , H01L31/111
摘要： An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors. In one embodiment, a feedback network includes a resistor connected between the output of a buffer driven by the transimpedance amplifier and an inverting input thereof, and a capacitor connected between the output and inverting input of the transimpedance amplifier to provide low noise, fast settling operation.
摘要翻译： 集成电路光电检测器包括跨阻抗放大器，其包括具有PNP发射极耦合晶体管的差分放大器级和仅由发射极耦合晶体管的基极电流偏置的PNP输入晶体管，以实现低输入偏置电流。 分别通过耦合在输入晶体管的基极和发射极之间的旁路电容来实现低噪声操作。 恒流源提供电流，该电流在电阻器两端产生小的基座电压，以偏置跨阻放大器的非反相输入，以避免低电平光信号的非线性放大。 正偏置N型保护桶围绕形成在P基板上的结隔离N区域中的光电检测器，以通过深穿透IR光收集在衬底中产生的电子，以防止它们引起放大误差。 在一个实施例中，反馈网络包括连接在由跨阻抗放大器驱动的缓冲器的输出与其反相输入之间的电阻器，以及连接在跨阻放大器的输出和反相输入端之间以提供低噪声，快速稳定操作 。
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公开(公告)号：US5592124A
公开(公告)日：1997-01-07
申请号：US494413
申请日：1995-06-26
摘要： An integrated circuit photodetector includes a transimpedance amplifier including a differential amplifier stage with PNP emitter-coupled transistors and a PNP input transistor which are biased only by base currents of the emitter-coupled transistors, to achieve low input bias current. Low noise operation is achieved by bypass capacitors coupled between the bases and emitters of the input transistors, respectively. A constant current source supplies a current which develops a small pedestal voltage across a resistor to bias the non-inverting input of the transimpedance amplifier so as to avoid nonlinear amplification of low level light signals. A positively biased N-type guard tub surrounds the photodetector, which is formed in a junction-isolated N region on a P substrate, to collect electrons generated in the substrate by deep-penetrating IR light to prevent them from causing amplification errors. In one embodiment, a feedback network includes a resistor connected between the output of a buffer driven by the transimpedance amplifier and an inverting input thereof, and a capacitor connected between the output and inverting input of the transimpedance amplifier to provide low noise, fast settling operation.
摘要翻译： 集成电路光电检测器包括跨阻抗放大器，其包括具有PNP发射极耦合晶体管的差分放大器级和仅由发射极耦合晶体管的基极电流偏置的PNP输入晶体管，以实现低输入偏置电流。 分别通过耦合在输入晶体管的基极和发射极之间的旁路电容来实现低噪声操作。 恒流源提供电流，该电流在电阻器两端产生小的基座电压，以偏置跨阻放大器的非反相输入，以避免低电平光信号的非线性放大。 正偏置N型保护桶围绕形成在P基板上的结隔离N区域中的光电检测器，以通过深穿透IR光收集在衬底中产生的电子，以防止它们引起放大误差。 在一个实施例中，反馈网络包括连接在由跨阻抗放大器驱动的缓冲器的输出与其反相输入之间的电阻器，以及连接在跨阻放大器的输出和反相输入端之间以提供低噪声，快速稳定操作 。
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3.发明授权Circuit technique for cancelling non-linear capacitor-induced harmonic distortion 失效用于消除非线性电容器引起的谐波失真的电路技术
公开(公告)号：US4999585A
公开(公告)日：1991-03-12
申请号：US432544
申请日：1989-11-06
IPC分类号： H03F1/32
CPC分类号： H03F1/32 , H03F2200/261
摘要： Circuitry for reducing harmonic distortion in an amplifier includes a first transistor having a first non-linear collector-to-substrate capacitance, a first load device coupled to a collector of the first transistor, a first current source coupled to an emitter of the first transistor, a first conductor conducting an input voltage coupled to a base of the first transistor, and a second conductor coupled to the first load device and conducting an output voltage of the amplifier. The first transistor produces a first non-linear current in the first non-linear collector-to-substrate capacitance in response to the input voltage. A second transistor has a second non-linear collector-to-substrate capacitance. A second current source is coupled to an emitter of the second transistor. The first conductor is coupled to apply the input voltage to a base of the second transistor. The second transistor produces a second non-linear current in the second non-linear collector-to-substrate capacitance in response to the input voltage. A current mirror receives a collector current of the second transistor. The current mirror produces in the second conductor a correction signal substantially equal and opposite to the first non-linear current.
摘要翻译： 用于减小放大器中的谐波失真的电路包括具有第一非线性集电极到衬底电容的第一晶体管，耦合到第一晶体管的集电极的第一负载装置，耦合到第一晶体管的发射极的第一电流源 传导耦合到第一晶体管的基极的输入电压的第一导体和耦合到第一负载装置并传导放大器的输出电压的第二导体。 第一晶体管响应于输入电压在第一非线性集电极到衬底电容中产生第一非线性电流。 第二晶体管具有第二非线性集电极到衬底电容。 第二电流源耦合到第二晶体管的发射极。 第一导体被耦合以将输入电压施加到第二晶体管的基极。 第二晶体管响应于输入电压在第二非线性集电极到基板电容中产生第二非线性电流。 电流镜接收第二晶体管的集电极电流。 电流镜在第二导体中产生与第一非线性电流基本相等和相反的校正信号。
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4.发明授权Programmable gain amplifier circuitry and method for biasing JFET gain switches thereof 失效用于偏置JFET增益开关的可编程增益放大器电路和方法
公开(公告)号：US5327098A
公开(公告)日：1994-07-05
申请号：US98845
申请日：1993-07-29
摘要： A circuit for reducing input offset error and improving gain switching speed in a programmable gain amplifier includes a level shifting buffer that senses a signal on a common mode conductor in a differential input stage of an operational amplifier, and shifts the level of that signal up to the level corresponding to a level of an input signal applied to a non-inverting input of the operational amplifier. If a gain select signal is at a first logic level, the voltage produced by the buffer is applied to a gate electrode of one of a plurality of gain switching JFETs coupling a gain network to the inverting input of the operational amplifier, turning that JFET on. If the gain select signal is at a second logic level, the output of the buffer is isolated from the gain switching JFET and a turn off voltage is applied to the gate of the gain switching JFET.
摘要翻译： 用于减小输入偏移误差并提高可编程增益放大器中的增益切换速度的电路包括电平移位缓冲器，其检测运算放大器的差分输入级中的共模导体上的信号，并将该信号的电平转移到 该电平对应于施加到运算放大器的非反相输入端的输入信号的电平。 如果增益选择信号处于第一逻辑电平，则由缓冲器产生的电压被施加到将增益网络耦合到运算放大器的反相输入端的多个增益切换JFET之一的栅电极，使该JFET导通 。 如果增益选择信号处于第二逻辑电平，则缓冲器的输出与增益切换JFET隔离，并且关断电压被施加到增益切换JFET的栅极。
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公开(公告)号：US4901031A
公开(公告)日：1990-02-13
申请号：US298116
申请日：1989-01-17
CPC分类号： H03F3/45278 , H03F3/45286 , H03F3/4586 , H03F2200/372 , H03F2203/45302 , H03F2203/45304 , H03F2203/45394 , H03F2203/45674 , H03F2203/45702
摘要： A common-base, source-driven differential amplifier achieves both high speed operation and low noise operation by providing an input stage including a pair of source follower JFETs that drive emitters of a pair of NPN input transistors having their bases connected together and to a bias circuit. The collectors of the NPN transistors each are connected to a corresponding load device and to a corresponding input of an output amplifier stage. The bias circuit includes a current source and a pair of diode-connected NPN transistors having their bases and collectors connected to the current source and to the bases of the input transistors. The emitters of the diode-connected NPN transistors are connected to sources of a second pair of source follower JFETs, the gates of which are connected to the input terminals.
摘要翻译： 通用基极源驱动差分放大器通过提供包括一对源极跟随器JFET的输入级来实现高速运算和低噪声运算，该对源极跟随器JFET驱动其基极连接在一起的一对NPN输入晶体管的发射极和偏置 电路。 NPN晶体管的集电极各自连接到相应的负载装置和输出放大器级的相应输入端。 偏置电路包括电流源和一对二极管连接的NPN晶体管，其基极和集电极连接到电流源和输入晶体管的基极。 二极管连接的NPN晶体管的发射极连接到第二对源极跟随器JFET的源极，其栅极连接到输入端子。
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公开(公告)号：US07425848B2
公开(公告)日：2008-09-16
申请号：US11383413
申请日：2006-05-15
申请人： Viola Schaffer , Rodney T. Burt , Jürgen Metzger
发明人： Viola Schaffer , Rodney T. Burt , Jürgen Metzger
IPC分类号： H03B1/00
CPC分类号： H03K19/017581
摘要： An integrated circuit driver structure, comprising an amplifier, a current mirror block and an external current set resistor, is provided that is digitally configurable to operate in a current output mode or in a voltage output mode with its output level controlled by an external voltage. The current mirror block comprises multiple current sources, all having the same gate bias supplied by the output of amplifier. At any time, at least one current source is connected to supply the reference current to resistor, while all other current sources are connected to mirror the reference current to the load current output towards the load. A current gain ratio is based on the number of current sources connected to supply resistor and the number connected to mirror the reference current.
摘要翻译： 提供了一种集成电路驱动器结构，其包括放大器，电流镜块和外部电流设置电阻器，其可数字配置以在电流输出模式或电压输出模式下工作，其输出电平由外部电压控制。 电流镜块包括多个电流源，全部具有由放大器的输出提供的相同的栅极偏置。 在任何时候，连接至少一个电流源以将参考电流提供给电阻器，而所有其他电流源连接到反向负载电流输出的参考电流。 电流增益比基于连接到电源电阻的电流源的数量和连接到镜像参考电流的数量。
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公开(公告)号：US5091657A
公开(公告)日：1992-02-25
申请号：US671342
申请日：1991-03-19
申请人： Rodney T. Burt
发明人： Rodney T. Burt
IPC分类号： H01L21/8234 , H01L27/088 , H03K17/0412 , H03K17/567 , H03K17/687
CPC分类号： H03K17/04123
摘要： A high speed, high current analog switching circuit includes a switch JFET having its drain electrode connected to an analog input voltage terminal and a source electrode connected to an analog output voltage terminal. The gate electrode of the JFET switch is connected to switching control circuitry. The analog switching circuit includes circuitry that prevents the source-gate PN junction of the switch JFET from ever being forward biased more than approximately 0.2 volts. This prevents the charge storage capacitance of that PN junction from ever increasing to such high values (e.g. 100 to 1000 picofarads) that discharging of the charge storage capacitance through the channel resistance of the switch JFET takes excessively long periods of time. Rapid equalization of the analog output voltage and analog input voltage to within approximately 10 microvolts of each other is thereby achieved.
摘要翻译： 高速大电流模拟开关电路包括开关JFET，其漏极连接到模拟输入电压端子，源电极连接到模拟输出电压端子。 JFET开关的栅电极连接到开关控制电路。 模拟开关电路包括防止开关JFET的源极 - PN PN结的正向偏压大于约0.2伏的电路。 这防止了PN结的电荷存储电容不断增加到通过开关JFET的沟道电阻对电荷存储电容进行放电所需的时间过长的高值（例如100至1000皮法）。 从而实现了将模拟输出电压和模拟输入电压的快速均衡彼此在大约10微伏之内。
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8.发明授权Isolation amplifier including precision voltage-to-duty-cycle converter and low ripple, high bandwidth charge balance demodulator 失效隔离放大器包括精密电压 - 占空比转换器和低纹波，高带宽电荷平衡解调器
公开(公告)号：US4843339A
公开(公告)日：1989-06-27
申请号：US114654
申请日：1987-10-28
CPC分类号： C08F220/04 , H03F3/387 , H03K7/08
摘要： An isolation amplifier includes a voltage-to-duty-cycle modulator, a non-galvanic isolation barrier, and a demodulator converting a duty-cycle-modulated signal transmitted across the isolation barrier to an analog voltage replica of the analog input voltage. The modulator circuit includes a first current switching means which produces a first current that is switched between positive and negative values in response to an output from a comparator that can be referenced to a noise-synchronized signal. The first current is summed with an input current and the difference is integrated and input to the comparator, the output of which produces the duty-cycle-modulated signal. The demodulator includes a second current switching circuit for producing a second current that is switched between positive and negative levels in response to the duty-cycle-modulated signal received across the isolation barrier and includes circuitry for algebraically summing the input current with the second current and integrating the result to produce the analog output voltage. The modulator circuit and demodulator circuits are fabricated on a single semiconductor area to produce the close matching between components of the first and second current switching circuits. The area is cut in half to produce two chips, which are connected to two isolation barrier capacitors. In the demodulator, a sample and hold circuit synchronized with the duty-cycle-modulated signal transmitted across the isolation barrier samples the output of the integrator.
摘要翻译： 隔离放大器包括电压 - 占空比调制器，非电流隔离屏障和将跨隔离屏障传输的占空比调制信号转换为模拟输入电压的模拟电压副本的解调器。 调制器电路包括第一电流开关装置，其响应于可以参考噪声同步信号的比较器的输出产生在正值和负值之间切换的第一电流。 第一个电流与输入电流相加，差值被积分并输入到比较器，比较器的输出产生占空比调制信号。 解调器包括第二电流切换电路，用于响应于在隔离屏障上接收的占空比调制信号产生在正电平和负电平之间切换的第二电流，并且包括用于将输入电流与第二电流进行代数求和的电路，以及 将结果积分以产生模拟输出电压。 调制器电路和解调器电路制造在单个半导体区域上，以产生第一和第二电流开关电路的部件之间的紧密匹配。 该区域被切成两半以产生两个芯片，它们连接到两个隔离屏蔽电容器。 在解调器中，与隔离屏障上传输的占空比调制信号同步的采样和保持电路对积分器的输出进行采样。
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公开(公告)号：US08072262B1
公开(公告)日：2011-12-06
申请号：US12803468
申请日：2010-06-28
申请人： Rodney T. Burt , Joy Y. Zhang
发明人： Rodney T. Burt , Joy Y. Zhang
IPC分类号： H03F1/02
CPC分类号： H03F3/005 , H03F3/38 , H03F2200/271
摘要： A chopper-stabilized circuit (1) includes pre-chopping circuitry (26) for chopping an input signal (Vin) at a first frequency to generate a first signal. Input chopping circuitry (9) chops the first signal at a second frequency substantially greater than the first frequency to produce a second signal. The first frequency is a sub-harmonic of the second frequency. Post-chopping circuitry (30) chops the second chopped signal at the first frequency to produce a third signal that is applied to an input of a signal conditioning circuit (2). The output chopping circuitry (10) chops an output of the signal conditioning circuit at the second frequency to generate a fourth signal. The fourth signal is filtered.
摘要翻译： 斩波稳定电路（1）包括用于以第一频率斩波输入信号（Vin）的预斩波电路（26）以产生第一信号。 输入斩波电路（9）以基本上大于第一频率的第二频率斩波第一信号以产生第二信号。 第一频率是第二频率的次谐波。 斩波电路（30）以第一频率切断第二斩波信号以产生施加到信号调理电路（2）的输入的第三信号。 输出斩波电路（10）以第二频率斩波信号调理电路的输出，以产生第四信号。 第四个信号被滤波。
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公开(公告)号：US06854076B2
公开(公告)日：2005-02-08
申请号：US09826405
申请日：2001-04-03
申请人： Rodney T. Burt , R. Mark Stitt
发明人： Rodney T. Burt , R. Mark Stitt
CPC分类号： H03F3/45973 , H03F3/45941 , H03F2200/261 , H03F2203/45538
摘要： A method and apparatus for auto-calibrating an electronic device without interrupting normal operation of the device. An electronic device configured as a high voltage difference amplifier is disclosed having a calibration circuit which couples a calibration excitation signal to a common-mode signal path of the difference amplifier. The difference amplifier includes a variable transfer function circuit which may be used to adjust the common-mode rejection of the difference amplifier. The calibration excitation signal may be a random, pseudo-random, out-of-band, or other frequency shaped signal generated in reference to a clock signal. A calibration error signal is detected from an output signal. The variable transfer function circuit can be adjusted in response to the detected error signal to reduce the calibration error signal. As a result, common-mode rejection errors of the difference amplifier may be reduced while the difference amplifier is coupled to an input signal source.
摘要翻译： 一种用于在不中断设备的正常操作的情况下自动校准电子设备的方法和装置。 公开了一种配置为高压差分放大器的电子设备，其具有将校准激励信号耦合到差分放大器的共模信号路径的校准电路。 差分放大器包括可用于调节差分放大器的共模抑制的可变传递函数电路。 校准激励信号可以是参考时钟信号产生的随机，伪随机，带外或其他频率信号。 从输出信号检测校准误差信号。 可以根据检测到的误差信号调整可变传递函数电路，以减少校准误差信号。 结果，差分放大器的共模抑制误差可以减小，而差分放大器耦合到输入信号源。
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