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    APPARATUS AND METHOD FOR REDUCED LOADING OF SIGNAL TRANSMISSION ELEMENTS
    2.
    发明申请
    APPARATUS AND METHOD FOR REDUCED LOADING OF SIGNAL TRANSMISSION ELEMENTS 有权
    用于减少信号传输元件负载的装置和方法

    公开(公告)号：US20060274681A1

    公开(公告)日：2006-12-07

    申请号：US10908959

    申请日：2005-06-02

    申请人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Daniel Storaska

    发明人： Louis Hsu ,  Karl Selander ,  Michael Sorna ,  Daniel Storaska

    IPC分类号： H04B1/58

    CPC分类号： G06F13/4072

    摘要： An apparatus is provided which includes a common signal node operable to conduct a first signal, a first circuit coupled to the common signal node to utilize the first signal and a signal-handling element coupled to the common signal node. The signal-handling element includes an isolating circuit coupled to the first conductor, a second conductor operable to conduct an output of the isolating circuit, and a signal-handling circuit coupled to the second conductor. The signal-handling circuit is operable to perform a signal-handling function in response to the output of the isolating circuit. By virtue of the isolating circuit, the signal-handling circuit and the first circuit are isolated from the second conductor and the signal-handling circuit. Preferably, the achieved isolation permits a communication signal included in the first signal to be conducted within a communication apparatus with less capacitance, and producing less return loss of that signal.

    摘要翻译： 提供一种装置，其包括可操作以传导第一信号的公共信号节点，耦合到公共信号节点以利用第一信号的第一电路和耦合到公共信号节点的信号处理元件。 信号处理元件包括耦合到第一导体的隔离电路，可操作以导通隔离电路的输出的第二导体和耦合到第二导体的信号处理电路。 信号处理电路可操作以响应于隔离电路的输出执行信号处理功能。 通过隔离电路，信号处理电路和第一电路与第二导体和信号处理电路隔离。 优选地，所实现的隔离允许包含在第一信号中的通信信号在具有较小电容的通信设备内传导，并且产生较小的该信号的回波损耗。

    Methods for forming co-planar wafer-scale chip packages
    3.
    发明申请
    Methods for forming co-planar wafer-scale chip packages 有权
    用于形成共面晶片级芯片封装的方法

    公开(公告)号：US20060110851A1

    公开(公告)日：2006-05-25

    申请号：US10994494

    申请日：2004-11-20

    申请人： Lloyd Burrell ,  Howard Chen ,  Louis Hsu ,  Wolfgang Sauter

    发明人： Lloyd Burrell ,  Howard Chen ,  Louis Hsu ,  Wolfgang Sauter

    IPC分类号： H01L21/48 ,  H01L21/50

    CPC分类号： H01L23/5389 ,  H01L21/52 ,  H01L23/147 ,  H01L23/5385 ,  H01L2221/68322 ,  H01L2221/68345 ,  H01L2924/0002 ,  H01L2924/1433 ,  H01L2924/00

    摘要： Economical methods for forming a co-planar multi-chip wafer-level packages are proposed. Partial wafer bonding and partial wafer dicing techniques are used to create chips as well as pockets. The finished chips are then mounted in the corresponding pockets of a carrier substrate, and global interconnects among the chips are formed on the top planar surface of the finished chips. The proposed methods facilitate the integration of chips fabricated with different process steps and materials. There is no need to use a planarization process such as chemical-mechanical polish to planarize the top surfaces of the chips. Since the chips are precisely aligned to each other and all the chips are mounted facing up, the module is ready for global wiring, which eliminates the need to flip the chips from an upside-down position.

    摘要翻译： 提出了用于形成共面多芯片晶片级封装的经济方法。 部分晶片接合和部分晶片切割技术用于制造芯片以及口袋。 然后将完成的芯片安装在载体基板的相应凹穴中，并且芯片之间的全局互连形成在成品芯片的顶部平坦表面上。 所提出的方法促进了用不同工艺步骤和材料制造的芯片的集成。 不需要使用诸如化学机械抛光剂的平面化处理来平坦化芯片的顶表面。 由于芯片精确地对准并且所有芯片都朝上安装，所以模块准备好进行全局布线，从而不需要将芯片从倒置的位置翻转。

    UNIVERSAL CMOS DEVICE LEAKAGE CHARACTERIZATION SYSTEM
    4.
    发明申请
    UNIVERSAL CMOS DEVICE LEAKAGE CHARACTERIZATION SYSTEM 有权
    通用CMOS器件泄漏特性系统

    公开(公告)号：US20070252613A1

    公开(公告)日：2007-11-01

    申请号：US11380515

    申请日：2006-04-27

    申请人： Louis Hsu ,  Edward Pillai ,  Joseph Natonio ,  James Rockrohr ,  David Hanson

    发明人： Louis Hsu ,  Edward Pillai ,  Joseph Natonio ,  James Rockrohr ,  David Hanson

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2884 ,  G01R31/3008 ,  G01R31/318577

    摘要： The invention provides a universal leakage monitoring system (ULMS) to measure a plurality of leakage macros during the development of a manufacturing process or a normal operation period. The ULMS characterizes the leakage of both n-type and p-type CMOS devices on the gate dielectric leakage, the sub-threshold leakage, and the reverse biased junction leakage, and the like. Testing is performed sequentially from the first test macro up to the last test macro using an on-chip algorithm. When the last test macro is tested, it scans the leakage data out.

    摘要翻译： 本发明提供了一种通用泄漏监测系统（ULMS），用于在开发制造过程或正常操作期期间测量多个泄漏宏。 ULMS表征了栅极电介质泄漏，亚阈值泄漏和反向偏置结漏电以及n型和p型CMOS器件的泄漏等。 使用片上算法从第一测试宏到最后一个测试宏顺序执行测试。 当测试最后一个测试宏时，会扫描泄漏数据。

    REPROGRAMMABLE ELECTRICAL FUSE
    6.
    发明申请
    REPROGRAMMABLE ELECTRICAL FUSE 审中-公开
    可折叠电气保险丝

    公开(公告)号：US20080023789A1

    公开(公告)日：2008-01-31

    申请号：US11834841

    申请日：2007-08-07

    申请人： Louis Hsu ,  Conal Murray ,  Chaudrasekhar Narayan ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Conal Murray ,  Chaudrasekhar Narayan ,  Chih-Chao Yang

    IPC分类号： H01L29/00

    CPC分类号： H01L23/5256 ,  G11C16/02 ,  G11C17/16 ,  G11C17/18 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention provides a reprogrammable electrically blowable fuse. The electrically blowable fuse is programmed using an electro-migration effect and is reprogrammed using a reverse electro-migration effect. The state (i.e., “opened” or “closed”) of the electrically blowable fuse is determined by a sensing system which compares a resistance of the electrically blowable fuse to a reference resistance.

    摘要翻译： 本发明提供一种可再编程的可电熔熔断器。 电可熔熔丝使用电迁移效应进行编程，并使用反向电迁移效应重新编程。 可电熔熔丝的状态（即“打开”或“关闭”）由将电可电熔丝的电阻与参考电阻进行比较的感测系统确定。

    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures
    7.
    发明申请
    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
    具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法

    公开(公告)号：US20070235833A1

    公开(公告)日：2007-10-11

    申请号：US11393142

    申请日：2006-03-30

    申请人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    发明人： Kangguo Cheng ,  Louis Hsu ,  Jack Mandelman

    IPC分类号： H01L29/00

    CPC分类号： H01L27/10841 ,  H01L27/10864

    摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

    摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。

    Dielectric interconnect structures and methods for forming the same
    8.
    发明申请
    Dielectric interconnect structures and methods for forming the same 有权
    介电互连结构及其形成方法

    公开(公告)号：US20070224801A1

    公开(公告)日：2007-09-27

    申请号：US11390390

    申请日：2006-03-27

    申请人： Chih-Chao Yang ,  Louis Hsu ,  Rajiv Joshi

    发明人： Chih-Chao Yang ,  Louis Hsu ,  Rajiv Joshi

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/76834 ,  H01L21/76814 ,  H01L21/76826 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846

    摘要： Dielectric interconnect structures and methods for forming the same are provided. Specifically, the present invention provides a dielectric interconnect structure having a noble metal layer (e.g., Ru, Ir, Rh, Pt, RuTa, and alloys of Ru, Ir, Rh, Pt, and RuTa) that is formed directly on a modified dielectric surface. In a typical embodiment, the modified dielectric surface is created by treating an exposed dielectric layer of the interconnect structure with a gaseous ion plasma (e.g., Ar, He, Ne, Xe, N2, H2, NH3, and N2H2). Under the present invention, the noble metal layer could be formed directly on an optional glue layer that is maintained only on vertical surfaces of any trench or via formed in the exposed dielectric layer. In addition, the noble metal layer may or may not be provided along an interface between the via and an internal metal layer.

    摘要翻译： 提供介电互连结构及其形成方法。 具体地说，本发明提供一种具有贵金属层（例如，Ru，Ir，Rh，Pt，RuTa以及Ru，Ir，Rh，Pt和RuTa的合金）的电介质互连结构，其直接形成在改性电介质上 表面。 在典型的实施例中，通过用气体离子等离子体（例如，Ar，He，Ne，Xe，N 2，H 2，NH 3和N 2 H 2）。 在本发明中，贵金属层可以直接形成在只保留在暴露的介电层中形成的任何沟槽或通孔的垂直表面上的任选的胶层上。 此外，贵金属层可以沿着通孔和内部金属层之间的界面设置也可以不设置。

    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer
    9.
    发明申请
    Electronic fuse with conformal fuse element formed over a freestanding dielectric spacer 失效
    具有保形熔丝元件的电子保险丝，形成在独立电介质垫片上

    公开(公告)号：US20070210890A1

    公开(公告)日：2007-09-13

    申请号：US11372387

    申请日：2006-03-09

    申请人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    发明人： Louis Hsu ,  Jack Mandelman ,  William Tonti ,  Chih-Chao Yang

    IPC分类号： H01H85/04

    CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  Y10T29/49107 ,  H01L2924/00

    摘要： An electronic fuse for an integrated circuit and a method of fabrication thereof are presented. The electronic fuse has a first terminal portion and a second terminal portion interconnected by a fuse element. The fuse element has a convex upper surface and a lower surface with a radius of curvature at a smallest surface area of curvature less than or equal to 100 nanometers. Fabricating the electronic fuse includes forming an at least partially freestanding dielectric spacer above a supporting structure, and then conformably forming the fuse element of the fuse over at least a portion of the freestanding dielectric spacer, with the fuse element characterized as noted above. The dielectric spacer may remain in place as a thermally insulating layer underneath the fuse element, or may be removed to form a void underneath the fuse element.

    摘要翻译： 本发明提供一种用于集成电路的电子熔断器及其制造方法。 电子熔断器具有由熔丝元件互连的第一端子部分和第二端子部分。 保险丝元件具有凸起的上表面和具有小于或等于100纳米的曲率的最小表面积的曲率半径的下表面。 制造电子熔断器包括在支撑结构之上形成至少部分独立的介电隔离物，然后在独立电介质隔离物的至少一部分上顺应地形成熔丝的熔丝元件，其中熔丝元件的特征如上所述。 电介质间隔物可以保留在熔丝元件下面的绝热层的适当位置，或者可以被去除以在熔丝元件下面形成空隙。