摘要:
A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
摘要:
A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
摘要:
A processing platform and a method of controlling power consumption of a central processing unit of the processing platform are presented. By operating the method the processing platform is able to set an upper performance state limit and a lower performance state limit. The upper performance state limit is based on a central processing unit activity rate value and the lower performance state limit is based on a minimum require of the operating system to perform operating system tasks. The performance state values are varying within a range of the lower and upper limits according to a power management policy.
摘要:
In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
摘要:
In some embodiments, a PPM interface may be provided with functionality to facilitate to an OS memory power state management for one or more memory nodes, regardless of a particular platform hardware configuration, as long as the platform hardware is in conformance with the PPM interface.
摘要:
In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
摘要:
In an embodiment, a processor includes multiple cores each to independently execute instructions and a power control unit (PCU) coupled to the plurality of cores to control power consumption of the processor. The PCU may include a mapping logic to receive a performance scale value from an operating system (OS) and to calculate a dynamic performance-frequency mapping based at least in part on the performance scale value. Other embodiments are described and claimed.
摘要:
According to some embodiments, a power budget allocation engine of a multi-component computer system may receive a power budget allocation adjustment request signal from a first component. Based on the received budget allocation adjustment request signal (and, in some embodiments, a component preference), the power budget allocation engine may determine whether to adjust a power budget allocation signal provided to the first component.
摘要:
A method and system to adjust a non-volatile cache associativity are described. In one embodiment, the method and system include determining a status of the system; and setting an associativity level of the non-volatile memory cache (NVC) of the system, based on that status of the system. In one embodiment, the non-volatile memory unit is a cache of the hard drive. Furthermore, in one embodiment, determining the status of the system includes determining whether the system is a mobile computer, and if so, determining whether the system is receiving power from a battery source or AC power from a wall outlet.
摘要:
According to some embodiments, a power budget allocation engine of a multi-component computer system may receive a power budget allocation adjustment request signal from a first component. Based on the received budget allocation adjustment request signal (and, in some embodiments, a component preference), the power budget allocation engine may determine whether to adjust a power budget allocation signal provided to the first component.