公开(公告)号：US20140131653A1

公开(公告)日：2014-05-15

申请号：US13675923

申请日：2012-11-13

Applicant: FENG-MING LEE ,  YU-YU LIN ,  MING-HSIU LEE

Inventor： FENG-MING LEE ,  YU-YU LIN ,  MING-HSIU LEE

IPC: H01L45/00 ,  G11C11/00

CPC classification number: G11C11/00 ,  H01L27/2409 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1266 ,  H01L45/145

Abstract: A programmable metallization device comprises a first electrode and a second electrode, and a dielectric layer, a conductive ion-barrier layer, and an ion-supplying layer in series between the first and second electrodes. In operation, a conductive bridge is formed or destructed in the dielectric layer to represent a data value using bias voltages having the same polarity, enabling the use of diode access devices. To form a conductive bridge, a bias is applied that is high enough to cause ions to penetrate the conductive ion-barrier layer into the dielectric layer, which then form filaments or bridges. To destruct the conductive bridge, a bias of the same polarity is applied that causes current to flow through the structure, while ion flow is blocked by the conductive ion-barrier layer. As a result of Joule heating, any bridge in the dielectric layer disintegrates.

Abstract translation: 可编程金属化器件包括在第一和第二电极之间串联的第一电极和第二电极以及电介质层，导电离子阻挡层和离子供给层。 在操作中，在电介质层中形成或破坏导电桥，以使用具有相同极性的偏置电压来表示数据值，从而能够使用二极管接入装置。 为了形成导电桥，施加足够高的偏压，使得离子将导电离子阻挡层穿透到电介质层中，然后形成细丝或桥。 为了破坏导电桥，施加相同极性的偏压，导致电流流过结构，同时离子流被导电离子阻挡层阻挡。 作为焦耳加热的结果，介电层中的任何桥分解。

公开(公告)号：US20100165711A1

公开(公告)日：2010-07-01

申请号：US12345384

申请日：2008-12-29

Applicant: MING-HSIU LEE

Inventor： MING-HSIU LEE

IPC: G11C11/00

CPC classification number: G11C13/0038 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/79

Abstract: Memory devices and methods for operating such devices are described herein. A method is described herein for operating a memory cell comprising phase change material and programmable to a plurality of resistance states including a high resistance state and a lower resistance state. The method comprises applying a first bias arrangement to the memory cell to establish the lower resistance state, the first bias arrangement comprising a first voltage pulse. The method further comprises determining whether the memory cell is in the lower resistance state, and if the memory cell is not in the lower resistance state then applying a second bias arrangement to the memory cell. The second bias arrangement comprises a second voltage pulse having a pulse height greater than that of the first voltage pulse.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文描述了一种用于操作包括相变材料并且可编程为包括高电阻状态和较低电阻状态的多个电阻状态的存储单元的方法。 该方法包括将第一偏置装置施加到存储器单元以建立较低电阻状态，第一偏置装置包括第一电压脉冲。 该方法还包括确定存储器单元是否处于较低电阻状态，并且如果存储单元不处于较低电阻状态，则向存储单元施加第二偏置布置。 第二偏置装置包括具有大于第一电压脉冲的脉冲高度的第二电压脉冲。

公开(公告)号：US20130343115A1

公开(公告)日：2013-12-26

申请号：US13601209

申请日：2012-08-31

Applicant: WEI-CHIH CHIEN ,  MING-HSIU LEE

Inventor： WEI-CHIH CHIEN ,  MING-HSIU LEE

IPC: H01L47/00 ,  G11C11/00

CPC classification number: H01L45/08 ,  G11C13/0007 ,  G11C13/0069 ,  G11C13/0097 ,  G11C29/50008 ,  G11C2029/5002 ,  G11C2213/72 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/1286 ,  H01L45/146

Abstract: A resistance memory cell is provided and includes a first electrode, a tungsten metal layer, a metal oxide layer, and a second electrode. The tungsten metal layer is disposed on the first electrode. The metal oxide layer is disposed on the tungsten metal layer. The second electrode includes a first connection pad, a second connection pad, and a bridge portion electrically connected between the first connection pad and the second connection pad. The bridge portion is disposed on the metal oxide layer or surrounds the metal oxide layer. The resistance memory cell adjusts a resistivity of the metal oxide layer through a first current path, passing through the metal oxide layer and the tungsten metal layer, or a second current path extending from the first connection pad to the second connection pad.

Abstract translation: 提供了一种电阻记忆单元，包括第一电极，钨金属层，金属氧化物层和第二电极。 钨金属层设置在第一电极上。 金属氧化物层设置在钨金属层上。 第二电极包括第一连接焊盘，第二连接焊盘和电连接在第一连接焊盘和第二连接焊盘之间的桥接部分。 桥接部分设置在金属氧化物层上或围绕金属氧化物层。 电阻存储单元通过穿过金属氧化物层和钨金属层的第一电流路径或从第一连接焊盘延伸到第二连接焊盘的第二电流路径来调节金属氧化物层的电阻率。

公开(公告)号：US20100110778A1

公开(公告)日：2010-05-06

申请号：US12266222

申请日：2008-11-06

Applicant: MING-HSIU LEE ,  MATTHEW J. BREITWISCH ,  CHUNG HON LAM

Inventor： MING-HSIU LEE ,  MATTHEW J. BREITWISCH ,  CHUNG HON LAM

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/009

Abstract: Memory devices and methods for operating such devices are described herein. A method as described herein includes applying a fixed sequence of voltage pulses across the memory cell of increasing pulse height to change the resistance state from the lower resistance state to the higher resistance state. The fixed sequence of voltage pulses cause increasing current through the phase change memory element until change to the higher resistance state occurs, and after the change the voltage pulses in the fixed sequence causing a voltage across the phase change memory element less than the threshold voltage.

Abstract translation: 这里描述了用于操作这样的设备的存储器件和方法。 本文所述的方法包括在增加脉冲高度的存储单元上施加固定的电压脉冲序列，以将电阻状态从较低电阻状态改变到较高电阻状态。 固定的电压脉冲序列导致增加的电流通过相变存储元件直到发生更高电阻状态的改变，并且在改变之后，固定序列中的电压脉冲导致相变存储元件上的电压小于阈值电压。

公开(公告)号：US20140119127A1

公开(公告)日：2014-05-01

申请号：US13661723

申请日：2012-10-26

Applicant: Hsiang-Lan Lung ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING-HSIU LEE

Inventor： Hsiang-Lan Lung ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING-HSIU LEE

IPC: G11C16/06

CPC classification number: G11C16/0475 ,  G11C16/10

Abstract: A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.

Abstract translation: 介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。 一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。 在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。 可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

公开(公告)号：US20130094273A1

公开(公告)日：2013-04-18

申请号：US13706001

申请日：2012-12-05

Applicant: WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

Inventor： WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

IPC: G11C5/06

CPC classification number: G11C5/06 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2454 ,  H01L27/249 ,  H01L28/24 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

Abstract: A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.

Abstract translation: 3D存储器件基于导电柱阵列和多个图案化的导体平面，其包括在左侧和右侧界面区域处邻近导电柱的左侧和右侧导体。 左侧和右侧界面区域中的存储元件包括可以通过内置自切换行为表征的可编程过渡金属氧化物或其它可编程电阻材料。 可以使用二维解码来选择导电柱，并且可以使用与左侧和右侧选择相结合的第三维度上的解码来选择多个平面中的左侧和右侧导体。

公开(公告)号：US20100314601A1

公开(公告)日：2010-12-16

申请号：US12484955

申请日：2009-06-15

Applicant: MING-HSIU LEE

Inventor： MING-HSIU LEE

IPC: H01L45/00 ,  H01L21/06

CPC classification number: H01L45/06 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1641

Abstract: A memory device having a phase change material element with a modified stoichiometry in the active region does not exhibit drift in set state resistance. A method for manufacturing the memory device includes first manufacturing an integrated circuit including an array of phase change memory cells with bodies of phase change material having a bulk stoichiometry; and then applying forming current to the phase change memory cells in the array to change the bulk stoichiometry in active regions of the bodies of phase change material to the modified stoichiometry, without disturbing the bulk stoichiometry outside the active regions. The bulk stoichiometry is characterized by stability under the thermodynamic conditions outside the active region, while the modified stoichiometry is characterized by stability under the thermodynamic conditions inside the active region.

Abstract translation: 具有在有源区域中具有改变的化学计量的相变材料元件的存储器件在设定状态电阻中不会出现漂移。 一种用于制造存储器件的方法包括：首先制造集成电路，该集成电路包括具有大体积化学计量的相变材料体的相变存储器单元的阵列; 然后将成形电流施加到阵列中的相变存储器单元，以将相变材料的主体的有源区域中的主体化学计量改变为改变的化学计量，而不会干扰有源区域外的主体化学计量。 主要化学计量学的特征在于在有源区域外的热力学条件下的稳定性，而改性的化学计量学的特征在于活性区域内的热力学条件下的稳定性。

公开(公告)号：US20100177553A1

公开(公告)日：2010-07-15

申请号：US12488795

申请日：2009-06-22

Applicant: MING-HSIU LEE ,  CHIEH-FANG CHEN ,  YEN-HAO SHIH ,  YU ZHU

Inventor： MING-HSIU LEE ,  CHIEH-FANG CHEN ,  YEN-HAO SHIH ,  YU ZHU

IPC: G11C11/00 ,  H01L47/00 ,  G11C11/34

CPC classification number: G11C13/0069 ,  G11C13/0004 ,  G11C2013/0071 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/79 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625

Abstract: Memory devices described herein are programmed and erased by physical segregation of an electrically insulating layer out of a memory material to establish a high resistance state, and by re-absorption of at least a portion of the electrically insulating layer into the memory material to establish a low resistance state. The physical mechanism of programming and erasing includes movement of structure vacancies to form voids, and/or segregation of doping material and bulk material, to create the electrically insulating layer consisting of voids and/or dielectric doping material along an inter-electrode current path between electrodes.

Abstract translation: 通过将电绝缘层从存储材料中物理分离出来以建立高电阻状态，并且通过将电绝缘层的至少一部分再吸收到存储材料中以建立 低电阻状态。 编程和擦除的物理机制包括结构空位的移动以形成空隙，和/或掺杂材料和体材料的偏析，以产生由空隙和/或介电掺杂材料构成的电绝缘层，沿着电极间电流通路 电极。

公开(公告)号：US20120320669A1

公开(公告)日：2012-12-20

申请号：US13161129

申请日：2011-06-15

Applicant: MING-HSIU LEE ,  CHIEH-FANG CHEN

Inventor： MING-HSIU LEE ,  CHIEH-FANG CHEN

IPC: G11C11/21

CPC classification number: G11C8/08 ,  G11C8/10 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0073

Abstract: A memory device is provided. The memory device includes a memory array; a first circuit electrically connected to the memory array, and causing the memory array to be operated in a first mode; and a second circuit electrically connected to the memory array, and causing the memory array to be operated in a second mode.

Abstract translation: 提供存储器件。 存储器件包括存储器阵列; 电连接到存储器阵列的第一电路，并使存储器阵列以第一模式工作; 以及电连接到存储器阵列的第二电路，并且使存储器阵列以第二模式工作。

公开(公告)号：US20110080780A1

公开(公告)日：2011-04-07

申请号：US12969526

申请日：2010-12-15

Applicant: MING-HSIU LEE ,  YI CHOU CHEN

Inventor： MING-HSIU LEE ,  YI CHOU CHEN

IPC: G11C11/00

CPC classification number: G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0092

Abstract: A method of programming a phase change device includes selecting a desired threshold voltage (Vth) and applying a programming pulse to a phase change material in the phase change device. The applying of the programming pulse includes applying a quantity of energy to the phase change material to drive at least a portion of this material above a melting energy level. A portion of the energy applied to the phase change material is allowed to dissipate below the melting energy level. The shape of the energy dissipation from the phase change material is controlled until the energy applied to the phase change material is less than a quenched energy level, to cause the phase change device to have the desired Vth. A remaining portion of the energy applied to the phase change material is allowed to dissipate to an environmental level.

Abstract translation: 编程相变装置的方法包括选择期望的阈值电压（Vth）并将编程脉冲施加到相变装置中的相变材料。 应用编程脉冲包括向相变材料施加一定量的能量以将该材料的至少一部分驱动在熔化能级以上。 施加到相变材料的能量的一部分被允许消散在熔融能级以下。 控制来自相变材料的能量耗散的形状，直到施加到相变材料的能量小于淬火能量水平，以使相变装置具有期望的Vth。 施加到相变材料的能量的剩余部分被允许消散到环境水平。