公开(公告)号：US08921975B2

公开(公告)日：2014-12-30

申请号：US13488870

申请日：2012-06-05

申请人： Felix P. Anderson ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Timothy S. Hayes ,  Donald R. Letourneau ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Felix P. Anderson ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Timothy S. Hayes ,  Donald R. Letourneau ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H01L21/768 ,  H01L23/525

CPC分类号： H01L21/76892 ,  H01L21/76838 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.

摘要翻译： 一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层， 连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。

公开(公告)号：US20120261813A1

公开(公告)日：2012-10-18

申请号：US13087449

申请日：2011-04-15

申请人： Felix P. Anderson ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Donald R. Letourneau ,  Thomas L. McDevitt

发明人： Felix P. Anderson ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Donald R. Letourneau ,  Thomas L. McDevitt

IPC分类号： H01L23/498 ,  G06F11/22 ,  H01L21/60

CPC分类号： H01L24/11 ,  H01L23/522 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/05571 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2224/81805

摘要： Disclosed is reinforced via farm interconnect structure for an integrated circuit chip that minimizes delamination caused by tensile stresses applied to the chip through lead-free C4 connections during thermal cycling. The reinforced via farm interconnect structure includes a plurality of vias electrically connecting metal wires within different wiring levels and, for reinforcement, further incorporates dielectric columns into the lower metal wire so that the areas around the metal-to-metal interface between the vias and the lower metal wire contain a relatively strong dielectric-to-dielectric interface. The reinforced via farm interconnect structure can be located in an area of the chip at risk for delamination and, for added strength, can have a reduced via density relative to conventional via farm interconnect structures located elsewhere on the chip. Also disclosed are a method of forming the reinforced via farm interconnect structure and a method of redesigning an integrated circuit chip to include reinforced via farm interconnect structure(s).

摘要翻译： 公开了通过用于集成电路芯片的农场互连结构来加强，其最小化在热循环期间通过无铅C4连接施加到芯片的拉伸应力引起的分层。 增强通孔农场互连结构包括多个通孔，电连接不同布线层内的金属线，并且为了加强，进一步将电介质柱并入下金属线，使得通孔和通孔之间的金属到金属界面周围的区域 下部金属线包含相当强的电介质至电介质界面。 增强的通孔农场互连结构可以位于芯片的具有分层风险的区域中，并且为了增加的强度，可以相对于位于芯片上其他地方的常规通孔农场互连结构，具有降低的通孔密度。 还公开了一种形成加强的通孔农场互连结构的方法和重新设计集成电路芯片以包括增强的农场互连结构的方法。

公开(公告)号：US20130320488A1

公开(公告)日：2013-12-05

申请号：US13488870

申请日：2012-06-05

申请人： Felix P. Anderson ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Timothy S. Hayes ,  Donald R. Letourneau ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Felix P. Anderson ,  Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Timothy S. Hayes ,  Donald R. Letourneau ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： H01L23/525 ,  H01L21/768

CPC分类号： H01L21/76892 ,  H01L21/76838 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor fuse device and a method of fabricating the fuse device including a last metal interconnect layer including at least two discrete metal conductors, an inter-level dielectric layer deposited over the last metal interconnect layer and the at least two discrete metal conductors, a thin wire aluminum fuse connecting the at least two discrete metal conductors, and a fuse opening above the aluminum fuse.

摘要翻译： 一种半导体熔丝器件和一种制造熔丝器件的方法，该熔丝器件包括最后的金属互连层，其包括至少两个分立的金属导体，沉积在最后的金属互连层和至少两个分立的金属导体上的层间电介质层， 连接至少两个分立的金属导体的线铝保险丝，以及铝保险丝上方的保险丝开口。

公开(公告)号：US06833720B1

公开(公告)日：2004-12-21

申请号：US10604572

申请日：2003-07-31

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Thomas L. McDevitt ,  Anthony K. Stamper

IPC分类号： G01R3102

CPC分类号： H01L22/34 ,  G01N27/205 ,  G01R31/2851 ,  G01R31/2896 ,  H01L23/564 ,  H01L2924/0002 ,  H01L2924/00

摘要： Electrical detection is provided for dicing damage to moisture barrier/edge seals of IC chips which include a low-K dielectric material, a moisture barrier/edge seal for the IC chip, and a moisture damage sensor circuit positioned on the IC chip in proximity to the moisture barrier/edge seal. One or a plurality of moisture barrier/edge seals can be positioned along peripheral edges of the IC chip, and one or more moisture damage sensor circuit(s) can be positioned between the plurality of moisture barrier/edge seal(s), or between an active area of the IC chip and the moisture barrier/edge seal(s), or on a peripheral area of the IC chip outside of the moisture barrier/edge seal(s). The sensor circuit can comprises a single or a plurality of, via chain(s) including a plurality of vias connected in series, or wire monitor circuit(s) extending in a serpentine conductive path through a plurality of wiring levels and vias, or interconnect(s), and the system can monitor the resistance(s) or leakage(s) or ratio(s) of parameters of the sensor circuit(s).

摘要翻译： 提供电检测，用于对包括低K介电材料，IC芯片的防潮/边缘密封以及位于IC芯片附近的水分损伤传感器电路的IC芯片的防潮/边缘密封的切割损伤 防潮/边缘密封。 一个或多个防潮/边缘密封件可以沿着IC芯片的周边边缘定位，并且一个或多个水分损伤传感器电路可以位于多个防潮层/边缘密封件之间，或者位于 IC芯片的有源区域和防潮/边缘密封件，或在防潮层/边缘密封件外部的IC芯片的周边区域上。 传感器电路可以包括单个或多个通孔链，其包括串联连接的多个通孔，或者通过多个布线层和通孔在蛇形导电路径中延伸的线监视器电路，或互连 并且系统可以监测传感器电路的参数的电阻或泄漏或比率。

公开(公告)号：US07521336B2

公开(公告)日：2009-04-21

申请号：US11931194

申请日：2007-10-31

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Stephen E. Luce ,  Thomas L. McDevitt ,  William T. Motsiff ,  Mark J. Pouliot ,  Jennifer C. Robbins

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Stephen E. Luce ,  Thomas L. McDevitt ,  William T. Motsiff ,  Mark J. Pouliot ,  Jennifer C. Robbins

IPC分类号： H01L21/46

CPC分类号： H01L23/585 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

摘要翻译： 使用在低K电介质材料中不形成诸如铜或银互连的自钝化氧化物层的金属互连形成在IC芯片上的集成电路（IC）的低K电介质材料的裂纹停止，以防止 在切割操作期间，由IC芯片的周边边缘形成的切屑和破裂引起的IC芯片的有源区的损坏。 形成作为沿着IC芯片的有效区域的外周边缘定位的金属堆叠的防潮层或边缘密封件。 裂纹停止部由位于IC芯片的外周上的防潮层/边缘密封件外部的至少一个沟槽或凹槽形成。

公开(公告)号：US07335577B2

公开(公告)日：2008-02-26

申请号：US11317042

申请日：2005-12-22

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Stephen E. Luce ,  Thomas L. McDevitt ,  William T. Motsiff ,  Mark J. Pouliot ,  Jennifer C. Robbins

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Stephen E. Luce ,  Thomas L. McDevitt ,  William T. Motsiff ,  Mark J. Pouliot ,  Jennifer C. Robbins

IPC分类号： H01L21/46

CPC分类号： H01L23/585 ,  H01L21/31111 ,  H01L21/32134 ,  H01L21/76838 ,  H01L21/78 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material to prevent damage to the active area of the IC chip caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.

摘要翻译： 使用在低K电介质材料中不形成诸如铜或银互连的自钝化氧化物层的金属互连形成在IC芯片上的集成电路（IC）的低K电介质材料的裂纹停止，以防止 在切割操作期间，由IC芯片的周边边缘形成的切屑和破裂引起的IC芯片的有源区的损坏。 形成作为沿着IC芯片的有效区域的外周边缘定位的金属堆叠的防潮层或边缘密封件。 裂纹停止部由位于IC芯片的外周上的防潮层/边缘密封件外部的至少一个沟槽或凹槽形成。

公开(公告)号：US20130234315A1

公开(公告)日：2013-09-12

申请号：US13414877

申请日：2012-03-08

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/498 ,  H01L21/768

CPC分类号： H01L22/30 ,  H01L22/12 ,  H01L23/49816 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05552 ,  H01L2224/05558 ,  H01L2224/05568 ,  H01L2224/05584 ,  H01L2224/05655 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13023 ,  H01L2224/13028 ,  H01L2224/13111 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/94 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/3841 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/00015 ,  H01L2224/13099 ,  H01L2224/05099 ,  H01L2224/05599 ,  H01L2924/01047 ,  H01L2924/01029

摘要： Structures and methods for detecting solder wetting of pedestal sidewalls. The structure includes a semiconductor wafer having an array of integrated circuit chips, each of the integrated circuit chips having an array of chip pedestals having respective chip solder columns on top of the chip pedestals, the pedestals spaced apart a first distance in a first direction and a spaced apart second distance in second direction perpendicular to the first direction; and at least one monitor structure disposed in different regions of the wafer from the integrated circuit chips, the monitor structure comprising at least a first pedestal and a first solder column on a top surface of the first pedestal and a second pedestal and a second solder column on a top surface of the second pedestal, the first and the second pedestals spaced apart a third distance, the third distance less than the first and the second distances.

摘要翻译： 用于检测基座侧壁焊料润湿的结构和方法。 该结构包括具有集成电路芯片阵列的半导体晶片，每个集成电路芯片具有芯片基座阵列，其具有位于芯片基座顶部的相应的芯片焊料柱，基座沿第一方向隔开第一距离;以及 在垂直于第一方向的第二方向上间隔开的第二距离; 以及设置在所述晶片与所述集成电路芯片的不同区域中的至少一个监视器结构，所述监视器结构至少包括在所述第一基座的顶表面上的第一基座和第一焊料柱，以及第二基座和第二焊接柱 在第二基座的顶表面上，第一和第二基座间隔第三距离，第三距离小于第一和第二距离。

公开(公告)号：US08513814B2

公开(公告)日：2013-08-20

申请号：US13098816

申请日：2011-05-02

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter ,  Timothy D. Sullivan

IPC分类号： H01L23/48

CPC分类号： H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L2224/02126 ,  H01L2224/02141 ,  H01L2224/02145 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/05572 ,  H01L2224/05664 ,  H01L2224/061 ,  H01L2224/13006 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/131 ,  H01L2224/141 ,  H01L2224/14104 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/05552

摘要： Structures are provided with raised buffer pads for solder bumps. Methods are also provided for forming the raised buffer pads for solder bumps. The method includes forming a raised localized buffer pad structure on a tensile side of a last metal layer of a solder bump connection. The raised localized buffer pad structure increases a height of a portion of a pad structure of the solder bump connection with respect to a compressive side of the last metal layer.

摘要翻译： 结构提供有用于焊料凸块的凸起缓冲垫。 还提供了用于形成用于焊料凸块的凸起缓冲垫的方法。 该方法包括在焊料凸块连接的最后金属层的拉伸侧上形成升高的局部缓冲垫结构。 凸起的局部缓冲垫结构相对于最后一个金属层的压缩侧增加焊料凸块连接的焊盘结构的一部分的高度。

公开(公告)号：US08373275B2

公开(公告)日：2013-02-12

申请号：US12021321

申请日：2008-01-29

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/485

CPC分类号： H01L24/11 ,  H01L2224/02125 ,  H01L2224/02126 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/10126 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05552

摘要： A fine pitch solder bump structure with a built-in stress buffer that is utilized in electronic packages, and a method of producing the fine pitch solder bump structure with built-in stress buffer. Employed is a very thick final passivation layer that is constituted of a polyimide as a so-called “cushion” for a minimal thickness of UBM (BLM) pad and solder material, while concurrently completely separating the resultingly produced polyimide islands, so that the polyimide material provides most of the physical height for the “standoff” of a modified C4 (controlled collapse chip connection) structure. In employing the polyimide material as the primary structural component of the vertical chip package interconnect in this particular inventive manner, the inherent stress buffering property of the polyimide material is utilized to full advantage by effectively reducing the high stresses encountered during chip manufacture processing steps, such as chip join, reflow, preconditioning and reliability thermal cycle stressing.

摘要翻译： 具有用于电子封装中的内置应力缓冲器的细间距焊料凸块结构以及具有内置应力缓冲器的细间距焊料凸块结构的制造方法。 采用非常厚的最终钝化层，其由作为UBM（BLM）焊盘和焊料材料的最小厚度的所谓的缓冲层的聚酰亚胺构成，同时完全分离得到的聚酰亚胺岛，使得聚酰亚胺材料提供 大部分物理高度用于修改C4（可控崩溃芯片连接）结构的对立。 在采用聚酰亚胺材料作为垂直芯片封装互连的主要结构部件时，通过有效降低芯片制造加工步骤中遇到的高应力，可以充分利用聚酰亚胺材料的固有应力缓冲性能， 作为芯片连接，回流，预处理和可靠性热循环应力。

公开(公告)号：US08299568B2

公开(公告)日：2012-10-30

申请号：US13028332

申请日：2011-02-16

申请人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

发明人： Timothy H. Daubenspeck ,  Jeffrey P. Gambino ,  Christopher D. Muzzy ,  Wolfgang Sauter

IPC分类号： H01L23/58

CPC分类号： H01L23/5258 ,  H01L23/5254 ,  H01L23/5256 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A conductor-filled damage propagation barrier is formed extending into a low-k dielectric layer between a fuse and an adjacent circuit element for preventing propagation of damage during a fuse blow operation. Conductor material filling the damage propagation barrier is formed from the same conductor layer as that used to form an interconnect structure.

摘要翻译： 导体填充的损伤传播屏障形成为延伸到保险丝和相邻电路元件之间的低k电介质层，以防止在保险丝熔断操作期间传播损坏。 填充损伤传播屏障的导体材料由与用于形成互连结构的导体层相同的导体层形成。