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    HV transistor structure and corresponding manufacturing method
    2.
    发明授权
    HV transistor structure and corresponding manufacturing method 有权
    HV晶体管结构及相应的制造方法

    公开(公告)号：US06278163B1

    公开(公告)日：2001-08-21

    申请号：US09224939

    申请日：1998-12-31

    申请人： Federico Pio ,  Carlo Riva

    发明人： Federico Pio ,  Carlo Riva

    IPC分类号： H01L31062

    CPC分类号： H01L29/66575 ,  H01L21/823418 ,  H01L21/823443 ,  H01L27/088 ,  H01L27/105 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/7833

    摘要： An HV transistor integrated in a semiconductor substrate with a first type of conductivity, comprising a gate region included between corresponding drain and source regions, and being of the type wherein at least said drain region is lightly doped with a second type of conductivity. The drain region comprises a contact region with the second type of conductivity but being more heavily doped, from which a contact pad extends.

    摘要翻译： 集成在具有第一类型导电性的半导体衬底中的HV晶体管，包括在相应的漏极和源极区域之间包括的栅极区域，并且其中至少所述漏极区域被轻掺杂第二类型的导电性。 漏极区域包括具有第二类型导电性的接触区域，但是其重新掺杂，接触焊盘从该区域延伸。

    Process for forming an edge structure to seal integrated electronic devices, and corresponding device
    3.
    发明授权
    Process for forming an edge structure to seal integrated electronic devices, and corresponding device 失效
    用于形成边缘结构以密封集成电子设备的过程以及相应的设备

    公开(公告)号：US6057591A

    公开(公告)日：2000-05-02

    申请号：US14437

    申请日：1998-01-27

    申请人： Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

    发明人： Camilla Calegari ,  Anna Carrara ,  Lorenzo Fratin ,  Carlo Riva

    IPC分类号： H01L23/28 ,  H01L21/316 ,  H01L21/8247 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L27/115 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792 ,  H01L23/29

    CPC分类号： H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/958

    摘要： A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material. The electronic circuit is of the type that calls for formation above the major surface of at least one dielectric multilayer. The dielectric multilayer includes a layer of amorphous planarizing material having a continuous portion extending between two contiguous areas with a more internal first area and a more external second area in the morphological structure. The device edge morphological structure includes in the substrate an excavation on the side of the major surface at the more internal first area of the morphological structure in a zone in which is present the continuous portion of the dielectric multilayer.

    摘要翻译： 一种用于形成器件边缘形态结构的方法，用于在半导体材料的衬底的主表面周围保护和密封电子电路。 电子电路是要求在至少一个电介质多层的主表面上形成的类型的电路。 电介质多层包括一层无定形平面化材料，其具有连续部分，该连续部分在形状结构中具有更内部的第一区域和更外部的第二区域的两个连续区域之间延伸。 设备边缘形态结构包括在基底中的形状结构的更内部的第一区域的主表面侧的开口，其中存在电介质多层的连续部分的区域。

    Method of manufacturing a matrix of memory cells having control gates
    5.
    发明授权
    Method of manufacturing a matrix of memory cells having control gates 失效
    具有控制门的存储器单元的矩阵的制造方法

    公开(公告)号：US5597750A

    公开(公告)日：1997-01-28

    申请号：US474735

    申请日：1995-06-07

    申请人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

    发明人： Federico Pio ,  Carlo Riva ,  Silvia Lucherini

    IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： H01L27/11526 ,  G11C16/04 ,  G11C16/0433 ,  H01L27/115 ,  H01L27/11541

    摘要： A circuit structure for a matrix of EEPROM memory cells, being of a type which comprises a matrix of cells including plural rows and columns, with each row being provided with a word line and a control gate line and each column having a bit line; the bit lines, moreover, are gathered into groups or bytes of simultaneously addressable adjacent lines. Each cell in the matrix incorporates a floating gate transistor which is coupled to a control gate, connected to the control gate line, and is connected serially to a selection transistor; also, the cells of each individual byte share their respective source areas, which areas are structurally independent for each byte and are led to a corresponding source addressing line extending along a matrix column.

    摘要翻译： 一种用于EEPROM存储器单元的矩阵的电路结构，其包括包括多行和列的单元矩阵，每行具有字线和控制栅极线，每列具有位线; 此外，位线被收集成同时可寻址的相邻线的组或字节。 矩阵中的每个单元都包含一个浮动栅极晶体管，它连接到控制栅极，连接到控制栅极线，并串联连接到选择晶体管; 每个单独字节的单元也共享它们各自的源区域，哪些区域对于每个字节在结构上是独立的，并且被引导到沿着矩阵列延伸的对应的源寻址行。

    Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells
    8.
    发明授权
    Process for the manufacture of a component to limit the programming voltage and to stabilize the voltage incorporated in an electric device with EEPROM memory cells 失效
    用于制造组件以限制编程电压并且使用EEPROM存储器单元稳定结合在电气设备中的电压的工艺

    公开(公告)号：US5322803A

    公开(公告)日：1994-06-21

    申请号：US946797

    申请日：1992-09-18

    申请人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

    发明人： Paolo Cappelletti ,  Giuseppe Corda ,  Paolo Ghezzi ,  Carlo Riva ,  Bruno Vajana

    IPC分类号： G11C17/00 ,  H01L21/329 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/866 ,  H01L21/266

    CPC分类号： H01L29/66106 ,  H01L27/115 ,  H01L27/11517 ,  Y10S148/174 ,  Y10S438/983

    摘要： The manufacturing process comprises a first step of formation of an N type sink on a single-crystal silicon substrate, a second step of formation of an active area on the surface of said sink, a third step of implantation of N- dopant in a surface region of the sink inside said active area, a fourth step of growth of a layer of gate oxide over said region with N- dopant, a fifth step of N+ implantation inside said N- region, a sixth step of P+ implantation in a laterally displaced position with respect to said N+ region and a seventh step of formation of external contacts for said N+ and P+ regions. There is thus obtained a zener diode limiter, having a cut-off voltage which is stable over time and not much dependent on temperature and which does not require the addition of process steps with respect to those usually necessary for the accomplishment of EEPROM memory cells.

    摘要翻译： 该制造方法包括在单晶硅衬底上形成N型吸收体的第一步骤，在所述吸收体的表面上形成有源区的第二步骤，在表面上注入N掺杂剂的第三步骤 在所述有源区域内的宿的区域，在所述区域上用N-掺杂剂生长栅极氧化物层的第四步骤，在所述N-区域内N +注入的第五步骤，P +植入在横向位移中的第六步骤 相对于所述N +区域的位置，以及形成所述N +和P +区域的外部触点的第七步骤。 因此，获得了具有截止电压的齐纳二极管限幅器，该截止电压随着时间而稳定，并且不依赖于温度，并且不需要相对于完成EEPROM存储器单元通常所需的那些处理步骤。

    EEPROM memory cell with improved protection against errors due to cell breakdown
    9.
    发明授权
    EEPROM memory cell with improved protection against errors due to cell breakdown 失效
    EEPROM存储器单元具有改进的防止由于单元断开引起的错误的保护

    公开(公告)号：US5107461A

    公开(公告)日：1992-04-21

    申请号：US549763

    申请日：1990-07-09

    申请人： Carlo Riva

    发明人： Carlo Riva

    IPC分类号： G11C29/00 ,  G11C29/04 ,  H01L21/8247 ,  H01L27/115

    CPC分类号： G11C29/74

    摘要： An electrically erasable programmable read only memory (EEPROM) memory cell with 100% redundancy includes two tunnel storage elements (10, 18; 26, 30) which are connected in parallel between a common source voltage (16) and an enabling transistor (22) which is controlled by a transfer terminal (24) and leads to a bit line (14), with respective sensing transistors (12, 28) arranged in series with respect to the storage elements. According to the invention, the cell furthermore includes an auxiliary enabling transistor (40) which is arranged in series with the source and is controlled by the transfer terminal.