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    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process
    1.
    发明授权
    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process 失效
    STI填充氧化物的氮化，以防止制造过程中STI填充氧化物的损失

    公开(公告)号：US07491563B2

    公开(公告)日：2009-02-17

    申请号：US11955751

    申请日：2007-12-13

    申请人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T Mo

    发明人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T Mo

    IPC分类号： H01L21/00 ,  H01L21/76

    CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481

    摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.

    摘要翻译： 一种用于半导体器件的改进的浅沟槽隔离（STI）结构的方法和结构。 STI结构包含STI填充物的氮氧化物顶层。 可选地，STI结构包括邻近硅沟槽壁的STI填充的氮氧化物边缘。 在硅沟槽壁的上边缘附近的氮氧化物边缘的区域包括与氮氧化物边缘的其它区域相比相对较厚并且含有较高浓度的氮的氧氮化物角。 氮氧化物的特征是限制了STI填充高度损失，并且还减少了STI填充物中由于氢氟酸蚀刻和其它制造工艺引起的硅衬底的形成。 限制STI填充高度损失和形成纹理改善了STI结构的功能。 形成STI结构的方法与包括化学机械抛光（CMP）在内的标准半导体器件制造工艺特别兼容，因为该方法包括使用纯二氧化硅STI填充和等离子体和热氮化工艺来形成氧氮化物顶层 和氮氧化物边缘，包括氮氧化物拐角，STI填充。

    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process
    2.
    发明授权
    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process 失效

    公开(公告)号：US07491964B2

    公开(公告)日：2009-02-17

    申请号：US10905683

    申请日：2005-01-17

    申请人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

    发明人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481

    摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.

    Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same
    4.
    发明授权
    Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same 失效
    集成多栅极电介质组成和厚度半导体芯片及其制造方法

    公开(公告)号：US07518145B2

    公开(公告)日：2009-04-14

    申请号：US11627001

    申请日：2007-01-25

    申请人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    发明人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    IPC分类号： H01L29/10

    CPC分类号： H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.

    摘要翻译： 一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。 该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。 电路包括非关键器件和形成为该非关键器件的一部分的氧化物。 高K电介质材料形成在衬底上，作为电路内关键器件的一部分。 在高K电介质材料和下层衬底之间提供氧化物基界面。 第二种方法形成氮化物或氧氮化物作为第一种材料。

    INTEGRATED MULTIPLE GATE DIELECTRIC COMPOSITION AND THICKNESS SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME
    5.
    发明申请
    INTEGRATED MULTIPLE GATE DIELECTRIC COMPOSITION AND THICKNESS SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME 失效
    集成多栅型电介质组合物和厚度半导体芯片及其制造方法

    公开(公告)号：US20080179714A1

    公开(公告)日：2008-07-31

    申请号：US11627001

    申请日：2007-01-25

    申请人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    发明人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    IPC分类号： H01L23/58 ,  H01L21/31

    CPC分类号： H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.

    摘要翻译： 一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。 该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。 电路包括非关键器件和形成为该非关键器件的一部分的氧化物。 高K电介质材料形成在衬底上，作为电路内关键器件的一部分。 在高K电介质材料和下层衬底之间提供氧化物基界面。 第二种方法形成氮化物或氧氮化物作为第一种材料。

    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES
    6.
    发明申请
    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES 审中-公开
    用于减少前浇口结构中顶部止点效应的方法

    公开(公告)号：US20080188089A1

    公开(公告)日：2008-08-07

    申请号：US11671668

    申请日：2007-02-06

    申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    IPC分类号： H01L21/31

    CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

    摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

    摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。

    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX)
    7.
    发明申请
    SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURES INCLUDING GRADIENT NITRIDED BURIED OXIDE (BOX) 有权
    半导体绝缘体（SOI）结构，包括梯度氮化氧化物（BOX）

    公开(公告)号：US20120049317A1

    公开(公告)日：2012-03-01

    申请号：US13290634

    申请日：2011-11-07

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L29/12

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。

    Selective post-doping of gate structures by means of selective oxide growth
    8.
    发明授权
    Selective post-doping of gate structures by means of selective oxide growth 失效
    通过选择性氧化物生长选择性地掺杂栅极结构

    公开(公告)号：US07288814B2

    公开(公告)日：2007-10-30

    申请号：US11268100

    申请日：2005-11-07

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Steven J. Holmes

    IPC分类号： H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/02131 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/266 ,  H01L21/316 ,  H01L21/31612 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method for doping a polysilicon gate conductor, without implanting the substrate in a manner that would effect source/drain formation is provided. The inventive method comprises forming at least one polysilicon gate region atop a substrate; forming oxide seed spacers abutting the polysilicon gate; forming source/drain oxide spacers selectively deposited on the oxide seed spacers by liquid phase deposition, and implanting at least one polysilicon gate region, wherein the source/drain oxide spacers protect an underlying portion of the substrate. Multiple gate regions may be processed on a single substrate using conventional patterning. A block-mask provided by patterned photoresist can be used prior to implantation to pre-select the substrate area for gate conductor doping with one dopant type.

    摘要翻译： 提供了掺杂多晶硅栅极导体而不以将影响源极/漏极形成的方式植入衬底的方法。 本发明的方法包括在基板顶上形成至少一个多晶硅栅极区域; 形成邻接所述多晶硅栅极的氧化物种子间隔物; 通过液相沉积选择性地沉积在氧化物种间隔物上的源极/漏极氧化物间隔区，以及注入至少一个多晶硅栅极区域，其中源极/漏极氧化物间隔物保护衬底的下面部分。 可以使用常规图案化在单个基板上处理多个栅极区域。 在植入之前可以使用由图案化的光致抗蚀剂提供的块掩模，以预先选择用于掺杂一种掺杂剂类型的栅极导体的衬底区域。

    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX)
    10.
    发明授权
    Semiconductor-on-insulator (SOI) structures including gradient nitrided buried oxide (BOX) 有权
    绝缘体上半导体（SOI）结构包括梯度氮化掩埋氧化物（BOX）

    公开(公告)号：US07396776B2

    公开(公告)日：2008-07-08

    申请号：US11483901

    申请日：2006-07-10

    申请人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    发明人： Anthony I. Chou ,  Toshiharu Furukawa ,  Wilfried Haensch ,  Zhibin Ren ,  Dinkar V. Singh ,  Jeffrey W. Sleight

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78603 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.

    摘要翻译： 绝缘体上半导体结构包括插入在基底半导体衬底和表面半导体层之间的掩埋电介质层。 掩埋介电层包括氧化物材料，其包括氮化物梯度，其在掩埋介电层的界面处与基底半导体衬底和表面半导体层中的至少一个相接触。 掩埋介质层与基底半导体衬底和表面半导体层中的至少一个的界面是突然的，提供小于约5原子层厚度的转变，并且具有小于约10埃的RMS界面粗糙度。 包含不含氮的氧化物介电材料的第二电介质层可位于掩埋介电层和表面半导体层之间。