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    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES
    1.
    发明申请
    METHOD FOR REDUCING TOP NOTCHING EFFECTS IN PRE-DOPED GATE STRUCTURES 审中-公开
    用于减少前浇口结构中顶部止点效应的方法

    公开(公告)号：US20080188089A1

    公开(公告)日：2008-08-07

    申请号：US11671668

    申请日：2007-02-06

    申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

    IPC分类号： H01L21/31

    CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

    摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

    摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。

    Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same
    3.
    发明授权
    Integrated multiple gate dielectric composition and thickness semiconductor chip and method of manufacturing the same 失效
    集成多栅极电介质组成和厚度半导体芯片及其制造方法

    公开(公告)号：US07518145B2

    公开(公告)日：2009-04-14

    申请号：US11627001

    申请日：2007-01-25

    申请人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    发明人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    IPC分类号： H01L29/10

    CPC分类号： H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.

    摘要翻译： 一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。 该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。 电路包括非关键器件和形成为该非关键器件的一部分的氧化物。 高K电介质材料形成在衬底上，作为电路内关键器件的一部分。 在高K电介质材料和下层衬底之间提供氧化物基界面。 第二种方法形成氮化物或氧氮化物作为第一种材料。

    INTEGRATED MULTIPLE GATE DIELECTRIC COMPOSITION AND THICKNESS SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME
    4.
    发明申请
    INTEGRATED MULTIPLE GATE DIELECTRIC COMPOSITION AND THICKNESS SEMICONDUCTOR CHIP AND METHOD OF MANUFACTURING THE SAME 失效
    集成多栅型电介质组合物和厚度半导体芯片及其制造方法

    公开(公告)号：US20080179714A1

    公开(公告)日：2008-07-31

    申请号：US11627001

    申请日：2007-01-25

    申请人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    发明人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

    IPC分类号： H01L23/58 ,  H01L21/31

    CPC分类号： H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.

    摘要翻译： 一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。 该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。 电路包括非关键器件和形成为该非关键器件的一部分的氧化物。 高K电介质材料形成在衬底上，作为电路内关键器件的一部分。 在高K电介质材料和下层衬底之间提供氧化物基界面。 第二种方法形成氮化物或氧氮化物作为第一种材料。

    Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs
    5.
    发明授权
    Method for avoiding oxide undercut during pre-silicide clean for thin spacer FETs 失效
    避免氧化物底切在薄间隔FET预硅化物清洗过程中的方法

    公开(公告)号：US07091128B2

    公开(公告)日：2006-08-15

    申请号：US11266855

    申请日：2005-11-04

    申请人： Atul C. Ajmera ,  Andres Bryant ,  Percy V. Gilbert ,  Michael A. Gribelyuk ,  Edward P. Maciejewski ,  Renee T. Mo ,  Shreesh Narasimha

    发明人： Atul C. Ajmera ,  Andres Bryant ,  Percy V. Gilbert ,  Michael A. Gribelyuk ,  Edward P. Maciejewski ,  Renee T. Mo ,  Shreesh Narasimha

    IPC分类号： H01L21/302

    CPC分类号： H01L21/02063 ,  H01L21/31116 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for forming a CMOS device in a manner so as to avoid dielectric layer undercut during a pre-silicide cleaning step is described. During formation of CMOS device comprising a gate stack on a semiconductor substrate surface, the patterned gate stack including gate dielectric below a conductor with vertical sidewalls, a dielectric layer is formed thereover and over the substrate surfaces. Respective nitride spacer elements overlying the dielectric layer are formed at each vertical sidewall. The dielectric layer on the substrate surface is removed using an etch process such that a portion of the dielectric layer underlying each spacer remains. Then, a nitride layer is deposited over the entire sample (the gate stack, the spacer elements at each gate sidewall, and substrate surfaces) and subsequently removed by an etch process such that only a portion of said nitride film (the “plug”) remains. The plug seals and encapsulates the dielectric layer underlying each said spacer, thus preventing the dielectric material from being undercut during the subsequent pre-silicide clean process. By preventing undercut, this invention also prevents the etch-stop film (deposited prior to contact formation) from coming into contact with the gate oxide. Thus, the integration of thin-spacer transistor geometries, which are required for improving transistor drive current, is enabled.

    摘要翻译： 描述了在预硅化物清洁步骤期间以避免电介质层底切的方式形成CMOS器件的方法。 在形成包括半导体衬底表面上的栅极堆叠的CMOS器件的情况下，图案化栅极堆叠包括在具有垂直侧壁的导体下方的栅极电介质，在衬底表面之上和之上形成介电层。 在每个垂直侧壁处形成覆盖在电介质层上的各种氮化物间隔元件。 使用蚀刻工艺去除衬底表面上的电介质层，使得保留每个间隔物下面的介电层的一部分。 然后，在整个样品（栅极堆叠，每个栅极侧壁和衬底表面处的间隔元件）上沉积氮化物层，然后通过蚀刻工艺去除，使得仅一部分所述氮化物膜（“插塞”） 遗迹。 插头密封并封装每个所述间隔件下面的电介质层，从而防止在随后的硅化物前处理过程中电介质材料被切削。 通过防止底切，本发明还防止蚀刻停止膜（在接触形成之前沉积）与栅极氧化物接触。 因此，能够实现提高晶体管驱动电流所需的薄间隔晶体管几何形状的集成。

    Forming shallow trench isolation without the use of CMP
    7.
    发明授权
    Forming shallow trench isolation without the use of CMP 失效
    形成浅沟槽隔离而不使用CMP

    公开(公告)号：US07071072B2

    公开(公告)日：2006-07-04

    申请号：US10710001

    申请日：2004-06-11

    申请人： Renee T. Mo ,  Shreesh Narasimha

    发明人： Renee T. Mo ,  Shreesh Narasimha

    IPC分类号： H01L21/76

    CPC分类号： H01L21/76283

    摘要： Shallow trench isolation structures are formed without CMP by depositing a thick pad nitride and depositing oxide trench fill material such that: a) the material in the trenches is above the silicon surface by a process margin that allows for removal of trench fill in subsequent front end steps so that the final trench fill level is substantially coplanar with the silicon; and b) the oxide on the interior walls is easily removed, so that the pad nitride is removed in a wet etch.

    摘要翻译： 通过沉积厚衬垫氮化物和沉积氧化物沟槽填充材料形成浅沟槽隔离结构，使得：a）沟槽中的材料在硅表面之上，具有允许在随后的前端去除沟槽填充的工艺余量 使得最终沟槽填充水平基本上与硅共面; 和b）内壁上的氧化物容易去除，使得衬垫氮化物在湿蚀刻中被去除。

    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process
    9.
    发明授权
    Nitridation of STI fill oxide to prevent the loss of STI fill oxide during manufacturing process 失效

    公开(公告)号：US07491964B2

    公开(公告)日：2009-02-17

    申请号：US10905683

    申请日：2005-01-17

    申请人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

    发明人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

    IPC分类号： H01L29/00

    CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481

    摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.