公开(公告)号：US07491964B2

公开(公告)日：2009-02-17

申请号：US10905683

申请日：2005-01-17

申请人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

发明人： Fred Buehrer ,  Anthony I. Chou ,  Toshiharu Furukawa ,  Renee T. Mo

IPC分类号： H01L29/00

CPC分类号： H01L21/76232 ,  H01L21/76224 ,  H01L21/823481

摘要： A method and structure for an improved shallow trench isolation (STI) structure for a semiconductor device. The STI structure incorporates an oxynitride top layer of the STI fill. Optionally, the STI structure incorporates an oxynitride margin of the STI fill adjacent the silicon trench walls. A region of the oxynitride margin near the upper edges of the silicon trench walls includes oxynitride corners that are relatively thicker and contain a higher concentration of nitrogen as compared to the other regions of the oxynitride margin. The oxynitride features limit the STI fill height loss and also reduce the formation of divots in the STI fill below the level of the silicon substrate cause by hydrofluoric acid etching and other fabrication processes. Limiting STI fill height loss and the formation of divots improves the functions of the STI structure. The method of forming the STI structure is particularly compatible with standard semiconductor device fabrication processes, including chemical mechanical polishing (CMP), because the method incorporates the use of a pure silicon dioxide STI fill and plasma and thermal nitridation processes to form the oxynitride top layer and oxynitride margin, including the oxynitride corners, of the STI fill.

公开(公告)号：US20080188089A1

公开(公告)日：2008-08-07

申请号：US11671668

申请日：2007-02-06

申请人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

发明人： Anthony I. Chou ,  Sadanand V. Deshpande ,  Renee T. Mo ,  Shreesh Narasimha ,  Katsunori Onishi ,  Dominic Schepis

IPC分类号： H01L21/31

CPC分类号： H01L21/32105 ,  H01L21/28035 ,  H01L21/28247

摘要： A method for reducing top notching effects in pre-doped gate structures includes subjecting an etched, pre-doped gate stack structure to a re-oxidation process, the re-oxidation process comprising a radical assisted re-oxidation process so as to result in the formation of an oxide layer over vertical sidewall and horizontal top surfaces of the etched gate stack structure. The resulting oxide layer has a substantially uniform thickness independent of grain boundary orientations of the gate stack structure and independent of the concentration and location of dopant material present therein.

摘要翻译： 用于减少预掺杂栅极结构中的顶部切口效应的方法包括将经蚀刻的预掺杂栅极堆叠结构进行再氧化处理，所述再氧化工艺包括自由基辅助再氧化工艺，以便导致 在蚀刻的栅堆叠结构的垂直侧壁和水平顶表面上形成氧化物层。 所得到的氧化物层具有与栅极堆叠结构的晶界取向无关的基本均匀的厚度，而与其中存在的掺杂剂材料的浓度和位置无关。

公开(公告)号：US20130264679A1

公开(公告)日：2013-10-10

申请号：US13440172

申请日：2012-04-05

申请人： Arvind Kumar ,  Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

发明人： Arvind Kumar ,  Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L29/86 ,  H01L21/02

CPC分类号： H01L23/5256 ,  H01L21/84 ,  H01L28/20 ,  H01L29/86 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure providing a precision resistive element and method of fabrication is disclosed. Polysilicon is embedded in a silicon substrate. The polysilicon may be doped to control the resistance. Embodiments may include resistors, eFuses, and silicon-on-insulator structures. Some embodiments may include non-rectangular cross sections.

摘要翻译： 公开了提供精密电阻元件的半导体结构和制造方法。 多晶硅嵌入在硅衬底中。 可以掺杂多晶硅以控制电阻。 实施例可以包括电阻器，eFuse和绝缘体上硅结构。 一些实施例可以包括非矩形横截面。

公开(公告)号：US07518145B2

公开(公告)日：2009-04-14

申请号：US11627001

申请日：2007-01-25

申请人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

发明人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L29/10

CPC分类号： H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.

摘要翻译： 一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。 该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。 电路包括非关键器件和形成为该非关键器件的一部分的氧化物。 高K电介质材料形成在衬底上，作为电路内关键器件的一部分。 在高K电介质材料和下层衬底之间提供氧化物基界面。 第二种方法形成氮化物或氧氮化物作为第一种材料。

公开(公告)号：US20080179714A1

公开(公告)日：2008-07-31

申请号：US11627001

申请日：2007-01-25

申请人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

发明人： Anthony I. Chou ,  Renee T. Mo ,  Shreesh Narasimha

IPC分类号： H01L23/58 ,  H01L21/31

CPC分类号： H01L21/28202 ,  H01L21/823462 ,  H01L21/823857 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method comprises forming a material over a substrate and patterning the material to remove portions of the material and expose an underlying portion of the substrate. The method further includes performing an oxidation process to form an oxide layer over the exposed portion of the substrate and at an interface between the material and the substrate. A circuit comprises a non-critical device and an oxide formed as part of this non-critical device. A high-K dielectric material is formed over a substrate as part of the critical device within the circuit. An oxide based interface is provided between the high-K dielectric material and an underlying substrate. A second method forms a nitride or oxynitride as the first material.

摘要翻译： 一种方法包括在衬底上形成材料并图案化材料以去除材料的部分并暴露衬底的下面部分。 该方法还包括进行氧化处理以在衬底的暴露部分和材料与衬底之间的界面处形成氧化物层。 电路包括非关键器件和形成为该非关键器件的一部分的氧化物。 高K电介质材料形成在衬底上，作为电路内关键器件的一部分。 在高K电介质材料和下层衬底之间提供氧化物基界面。 第二种方法形成氮化物或氧氮化物作为第一种材料。

公开(公告)号：US08507992B2

公开(公告)日：2013-08-13

申请号：US13048170

申请日：2011-03-15

申请人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

发明人： Renee T. Mo ,  Huiming Bu ,  Michael P. Chudzik ,  William K. Henson ,  Mukesh V. Khare ,  Vijay Narayanan

IPC分类号： H01L21/70

CPC分类号： H01L21/823807 ,  H01L21/28097 ,  H01L21/28194 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/1054 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66651 ,  H01L29/78

摘要： A method of forming a semiconductor device is provided that includes forming a Ge-containing layer atop a p-type device regions of the substrate. Thereafter, a first dielectric layer is formed in a second portion of a substrate, and a second dielectric layer is formed overlying the first dielectric layer in the second portion of the substrate and overlying a first portion of the substrate. Gate structures may then formed atop the p-type device regions and n-type device regions of the substrate, in which the gate structures to the n-type device regions include a rare earth metal.

摘要翻译： 提供一种形成半导体器件的方法，包括在基板的p型器件区域的顶部形成含Ge层。 此后，在衬底的第二部分中形成第一电介质层，并且在衬底的第二部分中覆盖第一介电层并覆盖衬底的第一部分上形成第二电介质层。 然后，栅极结构可以形成在衬底的p型器件区域和n型器件区域的顶部，其中n型器件区域的栅极结构包括稀土金属。

公开(公告)号：US20120149159A1

公开(公告)日：2012-06-14

申请号：US13397865

申请日：2012-02-16

申请人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

发明人： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

公开(公告)号：US20110227171A1

公开(公告)日：2011-09-22

申请号：US13150378

申请日：2011-06-01

申请人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

发明人： Michael P. Chudzik ,  William K. Henson ,  Renee T. Mo ,  Jeffrey Sleight

IPC分类号： H01L29/51

CPC分类号： H01L29/517 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/513 ,  H01L29/518

摘要： A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.

摘要翻译： 公开了一种与相邻氧化物隔离区域具有最小重叠的高k电介质和金属栅极叠层及相关方法。 栅堆叠的一个实施例包括高介电常数（高k）电介质层，调谐层和位于由衬底中的氧化物隔离区限定的有源区上的金属层，其中高k的外边缘 电介质层，调谐层和金属层与氧化物隔离区重叠小于约200纳米。 栅极堆叠和相关方法通过限制栅极堆叠和相邻氧化物隔离区域之间的重叠区域的量来消除短沟道器件中的再生长效应。

公开(公告)号：US07843007B2

公开(公告)日：2010-11-30

申请号：US12539842

申请日：2009-08-12

申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/517 ,  H01L21/823864 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4908 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6656

摘要： A method is disclosed to reduce parasitic capacitance in a metal high dielectric constant (MHK) transistor. The method includes forming a MHK gate stack upon a substrate, the MHK gate stack having a bottom layer of high dielectric constant material, a middle layer of metal, and a top layer of one of amorphous silicon or polycrystalline silicon. The method further forms a depleted sidewall layer on sidewalls of the MHK gate stack so as to overlie the middle layer and the top layer, and not the bottom layer. The depleted sidewall layer is one of amorphous silicon or polycrystalline silicon. The method further forms an offset spacer layer over the depleted sidewall layer and over exposed surfaces of the bottom layer.

摘要翻译： 公开了一种降低金属高介电常数（MHK）晶体管中的寄生电容的方法。 该方法包括在衬底上形成MHK栅极堆叠，MHK栅极堆叠层具有高介电常数材料的底层，中间金属层和非晶硅或多晶硅之一的顶层。 该方法进一步在MHK栅极堆叠的侧壁上形成耗尽的侧壁层，以覆盖中间层和顶层而不是底层。 耗尽的侧壁层是非晶硅或多晶硅之一。 该方法还在耗尽的侧壁层上方和底层的暴露表面之上形成偏移间隔层。

公开(公告)号：US20100044805A1

公开(公告)日：2010-02-25

申请号：US12609555

申请日：2009-10-30

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。