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    List sort static random access memory
    1.
    发明授权
    List sort static random access memory 有权
    列表排序静态随机存取存储器

    公开(公告)号：US09384824B2

    公开(公告)日：2016-07-05

    申请号：US14396331

    申请日：2012-07-10

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C15/04 ,  G11C19/28 ,  G11C11/412

    CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C15/04 ,  G11C19/28

    摘要： A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.

    摘要翻译： 列表排序静态随机存取存储器（LSSRAM）单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元和用于可选地切换LSSRAM的动态/静态（D / S）模式选择器 动态存储模式和静态存储模式之间的单元格。 所述LSSRAM单元还包括交换选择器，用于在所述交换选择器被激活时在所述动态存储模式期间与存储在相邻存储器单元中的数据交换所存储的数据;以及数据比较器，用于将所述SRAM单元中存储的数据与所述数据进行比较 存储在相邻存储单元中并且根据比较的结果激活交换选择器。

    Connection and addressing of multi-plane crosspoint devices
    2.
    发明授权
    Connection and addressing of multi-plane crosspoint devices 有权
    多平面交叉点设备的连接和寻址

    公开(公告)号：US08542515B2

    公开(公告)日：2013-09-24

    申请号：US13384872

    申请日：2010-04-30

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C5/06

    CPC分类号： H01L27/101 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    摘要： A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices.

    摘要翻译： 多平面电路结构至少具有第一电路平面和第二电路平面，并且每个电路平面具有多个行线段，多个列线段和在行的交叉处形成的多个交叉点设备 线段和列线段。 行和列线段具有用于在其上形成预选数量的交叉点设备的段长度。 第二电路平面中的每行线段在第一电路平面中与行方向和列方向上没有偏移连接到行线段，并且第二电路平面中的每列线段连接到列线 在行方向和列方向上具有偏移长度的第一电路平面中的段。 偏移长度对应于预选数量的交叉点设备的一半。

    READING A MEMORY ELEMENT WITHIN A CROSSBAR ARRAY
    4.
    发明申请
    READING A MEMORY ELEMENT WITHIN A CROSSBAR ARRAY 有权
    在十字架阵列中读取记忆元素

    公开(公告)号：US20110292712A1

    公开(公告)日：2011-12-01

    申请号：US12787857

    申请日：2010-05-26

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/062 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2213/77

    摘要： A method for reading a memory element within a crossbar array, the method including selecting a column line connected to a target memory element of the crossbar array by applying a supply voltage to a source follower, a gate terminal of the source follower connected to the column line; applying bias voltages to row lines of the crossbar array; storing an output voltage of the source follower in a storage element; applying a sense voltage to a row line connected to the target memory element; and outputting a difference between the voltage stored in the storage element and an output voltage of the source follower while the sense voltage is applied to the row line.

    摘要翻译： 一种用于读取交叉开关阵列内的存储元件的方法，所述方法包括通过向源极跟随器施加电源电压来选择连接到所述交叉开关阵列的目标存储器元件的列线，所述源极跟随器的栅极端子连接到所述列 线; 向所述交叉开关阵列的行线施加偏置电压; 将源极跟随器的输出电压存储在存储元件中; 对连接到目标存储元件的行线施加感测电压; 并且当所述感测电压被施加到所述行线时，输出存储在所述存储元件中的电压与所述源极跟随器的输出电压之间的差。

    Series diode thermally assisted MRAM
    5.
    发明申请
    Series diode thermally assisted MRAM 有权
    串联二极管热辅助MRAM

    公开(公告)号：US20060215444A1

    公开(公告)日：2006-09-28

    申请号：US11089688

    申请日：2005-03-24

    申请人： Frederick Perner ,  Janice Nickel ,  Lung Tran

    发明人： Frederick Perner ,  Janice Nickel ,  Lung Tran

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C11/1675

    摘要： An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.

    摘要翻译： 提供信息存储装置。 信息存储装置可以是包括自旋相关隧道（SDT）结或磁存储元件的电阻交叉点阵列的磁性随机存取存储器（MRAM）装置，其中字线沿着沿着SDT结的行和沿着 SDT路口的列。 本设计包括与相关联的磁存储元件串联连接的多个加热元件，每个加热元件包括二极管。 施加到磁存储元件和相关联的加热元件的电压导致反向电流流过二极管，从而从二极管产生热量并加热磁存储元件，从而有助于器件的写入功能。

    Method and apparatus for multi-plane MRAM
    6.
    发明申请
    Method and apparatus for multi-plane MRAM 有权
    多平面MRAM的方法和装置

    公开(公告)号：US20060050552A1

    公开(公告)日：2006-03-09

    申请号：US10934243

    申请日：2004-09-03

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C11/14

    CPC分类号： H01L27/228 ,  G11C11/15 ,  G11C11/16

    摘要： A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device. The method of fabricating the memory device includes fabricating a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, fabricating a second layer of MRAM memory cells over the first layer of MRAM memory cells, and fabricating a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device.

    摘要翻译： 存储器件包括根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储器单元的第一层上制造的第二层MRAM存储器单元，以及与MRAM存储器的第一层相关联的公共连接 单元和有助于存储器件操作的第二层MRAM存储器单元。 制造存储器件的方法包括制造根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储单元的第一层上制造第二层MRAM存储器单元，以及制造与第一层MRAM存储单元相关联的公共连接 MRAM存储器单元的层和有助于存储器件的操作的MRAM存储器单元的第二层。

    Light emitting device with adaptive intensity control
    7.
    发明申请
    Light emitting device with adaptive intensity control 审中-公开
    具有自适应强度控制的发光装置

    公开(公告)号：US20060007220A1

    公开(公告)日：2006-01-12

    申请号：US10861035

    申请日：2004-06-04

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G09G5/00

    CPC分类号： G09G3/20 ,  G09G2360/142

    摘要： A light emitting device with adaptive intensity control. In a particular embodiment, there is an active display pixel providing a light. At least a portion of the provided light is incident upon a photodetector optically coupled to the display pixel, the photodetector providing an electrical feedback signal in response to the light. A feedback controlled intensity controller electrically coupled to the photodetector and an electrical switch coupled to the active display pixel are also provided. The feedback controlled intensity controller further receives an electrical reference signal. The feedback controlled intensity controller opens and closes the switch depending upon the relationship of the feedback signal to the reference signal.

    摘要翻译： 具有自适应强度控制的发光器件。 在特定实施例中，存在提供光的主动显示像素。 所提供的光的至少一部分入射到光耦合到显示像素的光电检测器上，光电检测器响应于光而提供电反馈信号。 还提供电耦合到光电检测器的反馈控制强度控制器和耦合到主动显示像素的电开关。 反馈控制强度控制器还接收电参考信号。 反馈控制强度控制器根据反馈信号与参考信号的关系打开和闭合开关。

    1R1D MRAM block architecture
    8.
    发明申请
    1R1D MRAM block architecture 有权
    1R1D MRAM块架构

    公开(公告)号：US20050195647A1

    公开(公告)日：2005-09-08

    申请号：US10794302

    申请日：2004-03-04

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C11/15 ,  G11C7/22 ,  G11C11/00 ,  G11C11/16 ,  G11C16/26 ,  H01L21/8246 ,  H01L27/105

    CPC分类号： G11C11/16

    摘要： This invention provides a 1R1D block architecture magnetic memory device. In a particular embodiment, a cross-point array of resistive devices is provided. Each resistive device is paired with an isolation device. A feedback controlled control circuit is coupled to the cross-point array. The control circuit establishes an equi-potential setting within the cross-point array, and recognizes a change in current when a selected resistive device within the cross-point array is asserted to a reference state. An associated method of use is further provided.

    摘要翻译： 本发明提供一种1R1D块架构磁存储器件。 在特定实施例中，提供了电阻器件的交叉点阵列。 每个电阻设备与隔离设备配对。 反馈控制控制电路耦合到交叉点阵列。 所述控制电路在所述交叉点阵列内建立等电位设置，并且当所述交叉点阵列内的所选择的电阻性设备被认定为参考状态时，识别电流的变化。 还提供了相关联的使用方法。

    Shared volatile and non-volatile memory
    9.
    发明授权
    Shared volatile and non-volatile memory 有权
    共享易失性和非易失性存储器

    公开(公告)号：US06894918B2

    公开(公告)日：2005-05-17

    申请号：US10697367

    申请日：2003-10-30

    申请人： Manish Sharma ,  Frederick Perner

    发明人： Manish Sharma ,  Frederick Perner

    IPC分类号： G06F12/16 ,  G11C11/00 ,  G11C11/15 ,  G11C11/22 ,  G11C11/404 ,  G11C11/405 ,  G11C14/00 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L43/08 ,  G11C11/25

    CPC分类号： G11C14/0036 ,  G11C11/005 ,  G11C11/404 ,  G11C11/405 ,  G11C14/00

    摘要： The invention includes an apparatus and a method that provides a memory back-up system. The memory back-up system includes a first memory cell, and a non-volatile memory cell that is interfaced to the first memory cell. Control circuitry allows data to be written to either the first memory cell or the non-volatile memory cell, and provides transfer of the data from either the first memory cell or the non-volatile memory cell, to the other of either the first memory cell or the non-volatile memory cell. The memory back-up system can also include a plurality of first memory cells, and a plurality of non-volatile memory cells that are interfaced to the first memory cells. Control circuitry allows data to be written to either the first memory cells or the non-volatile memory cells, and that provides transfer of the data from either the first memory cells or the non-volatile memory cells, to the other of either the first memory cells or the non-volatile memory cells.

    摘要翻译： 本发明包括提供存储器备份系统的装置和方法。 存储器备份系统包括第一存储器单元和与第一存储器单元接口的非易失性存储器单元。 控制电路允许将数据写入第一存储器单元或非易失性存储单元，并且将数据从第一存储器单元或非易失性存储单元传送到第一存储单元 或非易失性存储单元。 存储器备份系统还可以包括多个第一存储器单元以及与第一存储器单元相连接的多个非易失性存储器单元。 控制电路允许将数据写入第一存储器单元或非易失性存储器单元，并且将数据从第一存储器单元或非易失性存储器单元传送到第一存储器 单元或非易失性存储单元。