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92 条记录 (耗时 0.037 秒)

    Memory array with write feedback
    2.
    发明授权
    Memory array with write feedback 有权
    具有写入反馈的存储器阵列

    公开(公告)号：US08331129B2

    公开(公告)日：2012-12-11

    申请号：US12875423

    申请日：2010-09-03

    申请人： Wei Yi ,  Frederick Perner ,  Matthew D. Pickett ,  Muhammad Shakeel Qureshi

    发明人： Wei Yi ,  Frederick Perner ,  Matthew D. Pickett ,  Muhammad Shakeel Qureshi

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C8/08 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2211/5624 ,  G11C2213/77

    摘要： A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

    摘要翻译： 具有写入反馈的存储器阵列包括与多条列线相交的许多行线，连接在行线之一和列线之一之间的存储元件，选择性地施加到行线之一的电气供应 ; 以及用于控制由电气供应提供的电气状况的反馈控制回路。 用于设置存储器阵列内的存储元件的状态的方法包括将电气条件施加到存储器阵列内的存储元件，感测存储元件的电阻状态，以及基于感测到的电阻状态来控制电气状态，从而导致 记忆元件达到目标电阻。

    MEMORY ARRAY WITH WRITE FEEDBACK
    5.
    发明申请
    MEMORY ARRAY WITH WRITE FEEDBACK 有权
    记忆阵列与写反馈

    公开(公告)号：US20120057390A1

    公开(公告)日：2012-03-08

    申请号：US12875423

    申请日：2010-09-03

    申请人： Wei Yi ,  Frederick Perner ,  Matthew D. Pickett ,  Muhammed Shakeel Qureshi

    发明人： Wei Yi ,  Frederick Perner ,  Matthew D. Pickett ,  Muhammed Shakeel Qureshi

    IPC分类号： G11C11/00

    CPC分类号： G11C5/063 ,  G11C8/08 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0066 ,  G11C2013/0076 ,  G11C2211/5624 ,  G11C2213/77

    摘要： A memory array with write feedback includes a number of row lines intersecting a number of column lines, a memory element connected between one of the row lines and one of the column lines, an electrical condition supply to be selectively applied to one of the row lines; and a feedback control loop to control an electrical condition supplied by the electrical condition supply. A method for setting the state of a memory element within a memory array includes applying an electrical condition to the memory element within the memory array, sensing a resistive state of the memory element, and controlling the electrical condition based on the sensed resistive state to cause the memory element to reach a target resistance.

    摘要翻译： 具有写入反馈的存储器阵列包括与多条列线相交的许多行线，连接在行线之一和列线之一之间的存储元件，选择性地施加到行线之一的电气供应 ; 以及用于控制由电气供应提供的电气状况的反馈控制回路。 用于设置存储器阵列内的存储元件的状态的方法包括将电气条件施加到存储器阵列内的存储元件，感测存储元件的电阻状态，以及基于所感测的电阻状态来控制电气状态，从而导致 记忆元件达到目标电阻。

    List sort static random access memory
    6.
    发明授权
    List sort static random access memory 有权
    列表排序静态随机存取存储器

    公开(公告)号：US09384824B2

    公开(公告)日：2016-07-05

    申请号：US14396331

    申请日：2012-07-10

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C15/04 ,  G11C19/28 ,  G11C11/412

    CPC分类号： G11C11/419 ,  G11C11/412 ,  G11C15/04 ,  G11C19/28

    摘要： A list sort static random access memory (LSSRAM) unit cell includes a static random access memory (SRAM) cell having a pair of cross-coupled elements to store data and a dynamic/static (D/S) mode selector to selectably switch the LSSRAM unit cell between a dynamic storage mode and a static storage mode. The LSSRAM unit cell further includes a swap selector to swap the stored data with data stored in an adjacent memory cell during the dynamic storage mode when the swap selector is activated, and a data comparator to compare the stored data in the SRAM cell with the data stored in the adjacent memory cell and to activate the swap selector according to a result of the comparison.

    摘要翻译： 列表排序静态随机存取存储器（LSSRAM）单元包括具有一对交叉耦合元件以存储数据的静态随机存取存储器（SRAM）单元和用于可选地切换LSSRAM的动态/静态（D / S）模式选择器 动态存储模式和静态存储模式之间的单元格。 所述LSSRAM单元还包括交换选择器，用于在所述交换选择器被激活时在所述动态存储模式期间与存储在相邻存储器单元中的数据交换所存储的数据;以及数据比较器，用于将所述SRAM单元中存储的数据与所述数据进行比较 存储在相邻存储单元中并且根据比较的结果激活交换选择器。

    Connection and addressing of multi-plane crosspoint devices
    7.
    发明授权
    Connection and addressing of multi-plane crosspoint devices 有权
    多平面交叉点设备的连接和寻址

    公开(公告)号：US08542515B2

    公开(公告)日：2013-09-24

    申请号：US13384872

    申请日：2010-04-30

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C5/06

    CPC分类号： H01L27/101 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    摘要： A multi-plane circuit structure has at least a first circuit plane and a second circuit plane, and each circuit plane has a plurality of row wire segments, a plurality of column wire segments, and a plurality of crosspoint devices formed at intersections of the row wire segments and the column wire segments. The row and column wire segments have a segment length for forming a preselected number of crosspoint devices thereon. Each row wire segment in the second circuit plane is connected to a row wire segment in the first circuit plane with no offset in a row direction and in a column direction, and each column wire segment in the second circuit plane is connected to a column wire segment in the first circuit plane with an offset length in both the row direction and the column direction. The offset length corresponds to half of the preselected number of crosspoint devices.

    摘要翻译： 多平面电路结构至少具有第一电路平面和第二电路平面，并且每个电路平面具有多个行线段，多个列线段和在行的交叉处形成的多个交叉点设备 线段和列线段。 行和列线段具有用于在其上形成预选数量的交叉点设备的段长度。 第二电路平面中的每行线段在第一电路平面中与行方向和列方向上没有偏移连接到行线段，并且第二电路平面中的每列线段连接到列线 在行方向和列方向上具有偏移长度的第一电路平面中的段。 偏移长度对应于预选数量的交叉点设备的一半。

    READING A MEMORY ELEMENT WITHIN A CROSSBAR ARRAY
    8.
    发明申请
    READING A MEMORY ELEMENT WITHIN A CROSSBAR ARRAY 有权
    在十字架阵列中读取记忆元素

    公开(公告)号：US20110292712A1

    公开(公告)日：2011-12-01

    申请号：US12787857

    申请日：2010-05-26

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C7/062 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2213/77

    摘要： A method for reading a memory element within a crossbar array, the method including selecting a column line connected to a target memory element of the crossbar array by applying a supply voltage to a source follower, a gate terminal of the source follower connected to the column line; applying bias voltages to row lines of the crossbar array; storing an output voltage of the source follower in a storage element; applying a sense voltage to a row line connected to the target memory element; and outputting a difference between the voltage stored in the storage element and an output voltage of the source follower while the sense voltage is applied to the row line.

    摘要翻译： 一种用于读取交叉开关阵列内的存储元件的方法，所述方法包括通过向源极跟随器施加电源电压来选择连接到所述交叉开关阵列的目标存储器元件的列线，所述源极跟随器的栅极端子连接到所述列 线; 向所述交叉开关阵列的行线施加偏置电压; 将源极跟随器的输出电压存储在存储元件中; 对连接到目标存储元件的行线施加感测电压; 并且当所述感测电压被施加到所述行线时，输出存储在所述存储元件中的电压与所述源极跟随器的输出电压之间的差。

    Series diode thermally assisted MRAM
    9.
    发明申请
    Series diode thermally assisted MRAM 有权
    串联二极管热辅助MRAM

    公开(公告)号：US20060215444A1

    公开(公告)日：2006-09-28

    申请号：US11089688

    申请日：2005-03-24

    申请人： Frederick Perner ,  Janice Nickel ,  Lung Tran

    发明人： Frederick Perner ,  Janice Nickel ,  Lung Tran

    IPC分类号： G11C11/00

    CPC分类号： G11C11/16 ,  G11C11/1675

    摘要： An information storage device is provided. The information storage device may be a magnetic random access memory (MRAM) device including a resistive cross point array of spin dependent tunneling (SDT) junctions or magnetic memory elements, with word lines extending along rows of the SDT junctions and bit lines extending along the columns of the SDT junctions. The present design includes a plurality of heating elements connected in series with associated magnetic memory elements, each heating element comprising a diode. Voltage applied to a magnetic memory element and associated heating element causes reverse current to flow through the diode, thereby producing heat from the diode and heating the magnetic memory element, thereby facilitating the write function of the device.

    摘要翻译： 提供信息存储装置。 信息存储装置可以是包括自旋相关隧道（SDT）结或磁存储元件的电阻交叉点阵列的磁性随机存取存储器（MRAM）装置，其中字线沿着沿着SDT结的行和沿着 SDT路口的列。 本设计包括与相关联的磁存储元件串联连接的多个加热元件，每个加热元件包括二极管。 施加到磁存储元件和相关联的加热元件的电压导致反向电流流过二极管，从而从二极管产生热量并加热磁存储元件，从而有助于器件的写入功能。

    Method and apparatus for multi-plane MRAM
    10.
    发明申请
    Method and apparatus for multi-plane MRAM 有权
    多平面MRAM的方法和装置

    公开(公告)号：US20060050552A1

    公开(公告)日：2006-03-09

    申请号：US10934243

    申请日：2004-09-03

    申请人： Frederick Perner

    发明人： Frederick Perner

    IPC分类号： G11C11/14

    CPC分类号： H01L27/228 ,  G11C11/15 ,  G11C11/16

    摘要： A memory device includes a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, a second layer of MRAM memory cells that is fabricated over the first layer of MRAM memory cells, and a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device. The method of fabricating the memory device includes fabricating a first layer of MRAM memory cells arranged in accordance with an MRAM architecture, fabricating a second layer of MRAM memory cells over the first layer of MRAM memory cells, and fabricating a common connection associated with the first layer of MRAM memory cells and the second layer of MRAM memory cells that facilitates operation of the memory device.

    摘要翻译： 存储器件包括根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储器单元的第一层上制造的第二层MRAM存储器单元，以及与MRAM存储器的第一层相关联的公共连接 单元和有助于存储器件操作的第二层MRAM存储器单元。 制造存储器件的方法包括制造根据MRAM架构布置的MRAM存储器单元的第一层，在MRAM存储单元的第一层上制造第二层MRAM存储器单元，以及制造与第一层MRAM存储单元相关联的公共连接 MRAM存储器单元的层和有助于存储器件的操作的MRAM存储器单元的第二层。