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    Method of manufacturing a semiconductor device with a pn junction provided through epitaxy
    1.
    发明授权
    Method of manufacturing a semiconductor device with a pn junction provided through epitaxy 失效
    通过外延生产具有pn结的半导体器件的方法

    公开(公告)号：US5915187A

    公开(公告)日：1999-06-22

    申请号：US768482

    申请日：1996-12-18

    申请人： Frederikus R. J. Huisman ,  Wiebe B. De Boer ,  Oscar J. A. Bulik ,  Ronald Dekker

    发明人： Frederikus R. J. Huisman ,  Wiebe B. De Boer ,  Oscar J. A. Bulik ,  Ronald Dekker

    IPC分类号： H01L21/205 ,  H01L21/302 ,  H01L21/56 ,  H01L21/78 ,  H01L29/864 ,  H01L29/93 ,  H01L21/20

    CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/78 ,  H01L29/93

    摘要： The invention relates to a method of manufacturing a semiconductor device with a pn junction, whereby an epitaxial layer (2) with a first zone (3) of a first conductivity type and with a second zone (4) of a second conductivity type opposed to the first is provided on a silicon substrate (1), a pn junction (5) being formed between the second and first zones (3, 4, respectively). According to the invention, the method is characterized in that the epitaxial layer (2) is provided by means of a CVD process at a temperature below 800.degree. C., the epitaxial layer (2) being provided in that first the first zone (3) and then the second zone (4) are epitaxially provided on the substrate (1), while no heat treatments at temperatures above 800.degree. C. take place after the epitaxial layer (2) has been provided. The measure according to the invention renders it possible to achieve properties of semiconductor devices manufactured in accordance with the invention, for example the capacitance-voltage (CV) relation of varicap diodes, within wide limits according to specifications. In addition, semiconductor devices manufactured by the method according to the invention require no post-diffusion or measurement steps in order to bring the properties of the semiconductor device up to specifications.

    摘要翻译： 本发明涉及制造具有pn结的半导体器件的方法，由此具有第一导电类型的第一区（3）和与第二导电类型相反的第二导电类型的第二区（4）的外延层（2） 第一设置在硅衬底（1）上，pn结（5）分别形成在第二区和第一区之间（3,4）。 根据本发明，该方法的特征在于外延层（2）通过CVD工艺在低于800℃的温度下提供，外延层（2）设置在第一区域（3） ），然后第二区（4）外延地设置在基板（1）上，而在提供了外延层（2）之后，在高于800℃的温度下不进行热处理。 根据本发明的措施使得可以根据本发明制造的半导体器件的性质，例如变容二极管的电容 - 电压（CV）关系在根据规格的宽范围内。 此外，通过根据本发明的方法制造的半导体器件不需要后扩散或测量步骤，以使半导体器件的性能达到规格。

    Manufacture of a semiconductor device with an epitaxial semiconductor zone
    2.
    发明授权
    Manufacture of a semiconductor device with an epitaxial semiconductor zone 失效
    具有外延半导体区域的半导体器件的制造

    公开(公告)号：US06368946B1

    公开(公告)日：2002-04-09

    申请号：US08822747

    申请日：1997-03-24

    申请人： Ronald Dekker ,  Cornelis E. Timmering ,  Doede Terpstra ,  Wiebe B. De Boer

    发明人： Ronald Dekker ,  Cornelis E. Timmering ,  Doede Terpstra ,  Wiebe B. De Boer

    IPC分类号： H01L21265

    CPC分类号： H01L29/66287 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02639

    摘要： A method of manufacturing a semiconductor device with an epitaxial semiconductor zone, whereby a first layer of insulating material, a first layer of non-monocrystalline silicon, and a second layer of insulating material are provided in that order on a surface of a silicon wafer, a window with a steep wall is etched through the second layer of insulating material and the first layer of non-monocrystalline silicon, the wall of the window is provided with a protective layer, the first insulating layer is selectively etched away within the window and below an edge of the first layer of non-monocrystalline silicon adjoining the window such that both the edge of the first layer of non-monocrystalline silicon itself and the surface of the wafer become exposed within the window and below said edge, semiconductor material is selectively deposited such that the epitaxial semiconductor zone is formed on the exposed surface of the wafer, and an edge of polycrystalline semiconductor material connected to the epitaxial semiconductor zone is formed on the exposed edge of the first layer of non-monocrystalline silicon, an insulating spacer layer is provided on the proctective layer on the wall of the window, and a second layer of non-monocrystalline silicon is deposited. The provision of a top layer of a material on which non-monocrystalline semiconductor material will grow during the selective deposition of the semiconductor material, which top layer is provided on the second layer of insulating material before the selective deposition of the semiconductor material, achieves that the selective deposition process can be better monitored.

    摘要翻译： 制造具有外延半导体区域的半导体器件的方法，其中第一绝缘材料层，第一非晶硅层和第二绝缘材料层依次设置在硅晶片的表面上， 通过绝缘材料的第二层和非单晶硅的第一层蚀刻具有陡峭壁的窗口，窗口的壁设置有保护层，第一绝缘层被选择性地蚀刻在窗口内并在窗口下方 邻接窗口的非单晶硅第一层的边缘使得第一层非单晶硅本身的边缘和晶片的表面两者都在窗口内部和所述边缘的下方露出，半导体材料被选择性地沉积如 外延半导体区形成在晶片的暴露表面上，并连接多晶半导体材料的边缘 在第一非晶硅单层的暴露边缘上形成外延半导体区，在窗口壁上的保护层上提供绝缘间隔层，并沉积第二层非单晶硅。 在选择性沉积半导体材料的选择性沉积期间，在半导体材料的选择性沉积之前，提供非单晶半导体材料将在其上生长的材料的顶层，该半导体材料在半导体材料的选择性沉积之前设置在第二绝缘材料层上， 可以更好地监测选择性沉积过程。

    SYSTEM-IN-PACKAGE PLATFORM FOR ELECTRONIC-MICROFLUIDIC DEVICES
    3.
    发明申请
    SYSTEM-IN-PACKAGE PLATFORM FOR ELECTRONIC-MICROFLUIDIC DEVICES 有权
    用于电子微流体装置的系统级封装平台

    公开(公告)号：US20130149215A1

    公开(公告)日：2013-06-13

    申请号：US13755293

    申请日：2013-01-31

    申请人： Ronald Dekker ,  Remco Henricus Wilhelmus Pijnenburg ,  Nicolaas Johannes Anthonius Van Veen

    发明人： Ronald Dekker ,  Remco Henricus Wilhelmus Pijnenburg ,  Nicolaas Johannes Anthonius Van Veen

    IPC分类号： H01L37/00 ,  B01L3/00

    CPC分类号： H01L37/00 ,  B01J2219/00783 ,  B01J2219/0095 ,  B01L3/502707 ,  B01L3/502715 ,  B01L2200/12 ,  B01L2200/14 ,  B01L2300/0645 ,  B01L2300/1827 ,  B01L2300/1883 ,  B01L2400/0415 ,  B81B2201/058 ,  B81C1/0023 ,  H01L2224/11 ,  Y10T436/11

    摘要： The present invention relates to an integrated electronic-microfluidic device an integrated electronic-microfluidic device, comprising a semiconductor substrate (106) on a first (122) support, an electronic circuit (102, 104) on a first semiconductor-substrate side of the semiconductor substrate, and a signal interface structure to an external device. The signal interface structure is arranged on the first semiconductor-substrate side and configured to receive electrical signals from the electronic circuit. A microfluidic structure (126) is formed in the semiconductor substrate, and is configured to confine a fluid and to allow a flow of the fluid to and from the microfluidic structure only on a second semiconductor-substrate side that is opposite to the first semiconductor-substrate side and faces away form the first support. The electronic-microfluidic device forms a flexible platform for the formation of various System-in-Package applications. It achieves a clear separation between electrical and wet-chemical interfaces. The claimed method for fabricating the device of the invention also allows a simple formation of thermally isolated microfluidic structures.

    摘要翻译： 本发明涉及一种集成电子微流体装置，集成的电子微流体装置，其包括在第一（122）支撑件上的半导体衬底（106），电子电路（102,104）的第一半导体衬底 半导体衬底和与外部设备的信号接口结构。 信号接口结构布置在第一半导体衬底侧并被配置为从电子电路接收电信号。 微流体结构（126）形成在半导体衬底中，并且被配置为限制流体并允许仅在与第一半导体衬底相反的第二半导体衬底侧上流体流过微流体结构， 衬底侧面和背面形成第一支撑件。 电子微流体装置形成用于形成各种系统级封装应用的灵活平台。 它实现了电气和湿化学界面之间的清晰分离。 所要求的制造本发明装置的方法还允许简单地形成热分离的微流体结构。

    CARDIOMYOCYTES-CONTAINING DEVICE AND METHOD FOR MANUFACTURING AND USING THE SAME
    5.
    发明申请
    CARDIOMYOCYTES-CONTAINING DEVICE AND METHOD FOR MANUFACTURING AND USING THE SAME 失效
    含有血小板活性的装置及其制造和使用方法

    公开(公告)号：US20120094323A1

    公开(公告)日：2012-04-19

    申请号：US13147607

    申请日：2010-02-02

    申请人： Ronald Dekker ,  Anja Van De Stolpe

    发明人： Ronald Dekker ,  Anja Van De Stolpe

    IPC分类号： C12Q1/18 ,  H01B13/00 ,  B05D5/00 ,  C12M1/34 ,  B05D1/36

    CPC分类号： G01N1/30 ,  C12N5/0657 ,  C12N2503/02 ,  C12N2535/10 ,  G01N33/5061

    摘要： Disclosed is a device for determining the cardiotoxicity of a chemical compound, comprising a substrate (10) carrying a deformable stack (34), said stack being partially detached from the substrate by a cavity (32) allowing an out-of-plane deformation of the stack, said stack comprising a first deformable layer (16), a second deformable layer (20) and a multi-electrode structure (18) sandwiched between the first and second deformable layers, the second deformable layer carrying a pattern of cardiomyocytes (28) adhered thereto; and a liquid container (26) mounted on the substrate for exposing the cardiomyocytes to the chemical compound. A method of manufacturing such a device is also disclosed. The present invention further relates to the use of the device for drug target discovery and/or drug development and a method for developing a disease model for a disease that is caused by or modified by stretching of cells, in particular a cardiac disease model.

    摘要翻译： 公开了一种用于确定化合物的心脏毒性的装置，包括承载可变形叠层（34）的基底（10），所述叠层通过空腔（32）部分地与基底分离，允许外部变形 所述堆叠包括夹在所述第一和第二可变形层之间的第一可变形层（16），第二可变形层（20）和多电极结构（18），所述第二可变形层承载心肌细胞图案（28 ） 和安装在基板上的用于将心肌细胞暴露于化合物的液体容器（26）。 还公开了制造这种装置的方法。 本发明还涉及该装置用于药物靶发现和/或药物开发的用途，以及用于开发由细胞拉伸，特别是心脏疾病模型引起或改变的疾病的疾病模型的方法。

    Deformable integrated circuit device
    6.
    发明授权
    Deformable integrated circuit device 有权
    可变形集成电路器件

    公开(公告)号：US07915707B2

    公开(公告)日：2011-03-29

    申请号：US12377673

    申请日：2007-08-07

    申请人： Ronald Dekker ,  Antoon Marie Henrie Tombeur ,  Theodoros Zoumpoulidis

    发明人： Ronald Dekker ,  Antoon Marie Henrie Tombeur ,  Theodoros Zoumpoulidis

    IPC分类号： H01L29/00

    CPC分类号： H01L23/49833 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated-circuit device includes a rigid substrate island having a main substrate surface with a circuit region circuit elements and at least one fold structure. The fold structure is attached to the substrate island and is unfoldable from a relaxed, folded state to a strained unfolded state. The fold structure contains at least one passive electrical component. The fold structure further has in its folded state at least one surface with an area vector that includes a non-vanishing area-vector component in a direction parallel to the main substrate surface, which area-vector component is diminished or vanishes when deforming the fold structure from the folded into the unfolded state.

    摘要翻译： 集成电路器件包括具有主衬底表面的刚性衬底岛，其具有电路区域电路元件和至少一个折叠结构。 折叠结构附接到基底岛，并且可以从松弛的折叠状态展开到应变展开状态。 折叠结构包含至少一个无源电组件。 折叠结构在其折叠状态下进一步具有面向向的至少一个表面，该区域向量在平行于主衬底表面的方向上包括非消失的面积 - 矢量分量，该区域 - 矢量分量在折叠变形时减少或消失 结构从折叠到展开状态。

    DEFORMABLE INTEGRATED CIRCUIT DEVICE
    9.
    发明申请
    DEFORMABLE INTEGRATED CIRCUIT DEVICE 有权
    可变电容集成电路

    公开(公告)号：US20100270640A1

    公开(公告)日：2010-10-28

    申请号：US12377673

    申请日：2007-08-07

    申请人： Ronald Dekker ,  Antoon Marie Henrie Tombeur ,  Theodoros Zoumpoulidis

    发明人： Ronald Dekker ,  Antoon Marie Henrie Tombeur ,  Theodoros Zoumpoulidis

    IPC分类号： H01L23/52 ,  H01L21/98

    CPC分类号： H01L23/49833 ,  H01L23/5387 ,  H01L2924/0002 ,  H01L2924/00

    摘要： An integrated-circuit device is provided, which comprises a rigid substrate island having a main substrate surface with a circuit region circuit elements and at least one fold structure. The fold structure is attached to the substrate island and is unfoldable from a relaxed, folded state to a strained unfolded state. The fold structure contains at least one passive electrical component. The fold structure further has in its folded state at least one surface with an area vector that includes a non-vanishing area-vector component in a direction parallel to the main substrate surface, which area-vector component is diminished or vanishes when deforming the fold structure from the folded into the unfolded state. The fold structure provided by the present invention allows fabricating the integrated-circuit device with small lateral extensions and thus takes up a particularly small amount of chip area, which reduces the cost per device.

    摘要翻译： 提供了一种集成电路器件，其包括具有主衬底表面的刚性衬底岛，其具有电路区域电路元件和至少一个折叠结构。 折叠结构附接到基底岛，并且可以从松弛的折叠状态展开到应变展开状态。 折叠结构包含至少一个无源电组件。 折叠结构在其折叠状态下进一步具有面向向的至少一个表面，该区域向量在平行于主衬底表面的方向上包括非消失的面积 - 矢量分量，该区域 - 矢量分量在折叠变形时减少或消失 结构从折叠到展开状态。 由本发明提供的折叠结构允许制造具有小横向延伸的集成电路器件，因此占据特别小量的芯片面积，这降低了每个器件的成本。

    IMPLANTABLE DEVICE WITH REMOTE READOUT
    10.
    发明申请
    IMPLANTABLE DEVICE WITH REMOTE READOUT 审中-公开
    具有远程读取功能的可移植设备

    公开(公告)号：US20100045440A1

    公开(公告)日：2010-02-25

    申请号：US12447678

    申请日：2007-10-31

    申请人： Remco Henricus Wilhelmus Pijnenburg ,  Youri Victorovitch Ponomarev ,  Matthias Merz ,  Ronald Dekker

    发明人： Remco Henricus Wilhelmus Pijnenburg ,  Youri Victorovitch Ponomarev ,  Matthias Merz ,  Ronald Dekker

    IPC分类号： H04Q5/22

    CPC分类号： G06K19/0723 ,  G06K7/0008

    摘要： The invention relates to a remotely readable electronic device (10), particularly an implantable device, with an O associated reader (20). The device comprises a resonance circuit (12) that can selectively be set into one of at least three different resonance states, wherein this state can wirelessly be sensed by the remote reader. In a particular embodiment, the resonance circuit (12) comprises two capacitors (C1, C2) that can selectively be connected or disconnected to the resonance circuit (12). The reader (20) preferably scans a given frequency range to detect spectral absorption patterns that correspond to certain resonance states of the resonance circuit (12).

    摘要翻译： 本发明涉及一种具有O相关阅读器（20）的远程可读电子设备（10），特别是可植入设备。 该装置包括可选择性地设置为至少三种不同共振状态中的一种的谐振电路（12），其中该状态可以由远程读取器无线地感测。 在一个具体实施例中，谐振电路（12）包括两个电容器（C1，C2），可以选择性地连接或断开到谐振电路（12）。 读取器（20）优选地扫描给定的频率范围以检测对应于谐振电路（12）的某些谐振状态的光谱吸收模式。