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    Mixed-signal circuitry
    2.
    发明授权
    Mixed-signal circuitry 有权
    混合信号电路

    公开(公告)号：US09112521B2

    公开(公告)日：2015-08-18

    申请号：US14473927

    申请日：2014-08-29

    Applicant: FUJITSU SEMICONDUCTOR LIMITED

    Inventor： Ian Juso Dedic ,  John James Danson

    IPC: H03M1/10 ,  H03M1/00 ,  H03M1/38 ,  H03M1/12 ,  H03M1/46

    CPC classification number: H03M1/002 ,  H03M1/1215 ,  H03M1/125 ,  H03M1/38 ,  H03M1/462

    Abstract: Mixed-signal circuitry, comprising: an array of ADC units configured to operate in a time-interleaved manner, and each operable in each of a series of time windows to convert an analog input value into a corresponding digital output value, each conversion comprising a sequence of sub-conversion operations, each successive sub-conversion operation of a sequence being triggered by completion of the preceding sub-conversion operation; and a controller, wherein: at least one of the ADC units is operable to act as a reporting ADC unit and indicate, for each of one or more monitored said conversions, whether or not a particular one of the sub-conversion operations completed during the time window concerned; and the controller is operable to consider at least one such indication and to control the circuitry in dependence upon the or each considered indication.

    Abstract translation: 混合信号电路，包括：被配置为以时间交织方式工作的ADC单元的阵列，并且每个可在一系列时间窗口中的每一个操作以将模拟输入值转换成相应的数字输出值，每个转换包括 子转换操作的顺序，通过完成前一次转换操作触发序列的每个连续子转换操作; 以及控制器，其中：所述ADC单元中的至少一个可操作以用作报告ADC单元，并针对一个或多个所监视的所述转换中的每一个指示在所述转换期间完成的所述子转换操作中的特定一个 时间窗; 并且所述控制器可操作以考虑至少一个这样的指示并且根据所述或每个所考虑的指示来控制所述电路。

    Circuitry and methods for use in mixed-signal circuitry
    4.
    发明授权
    Circuitry and methods for use in mixed-signal circuitry 有权
    用于混合信号电路的电路和方法

    公开(公告)号：US08976050B1

    公开(公告)日：2015-03-10

    申请号：US14025303

    申请日：2013-09-12

    Applicant: Fujitsu Semiconductor Limited

    Inventor： Ian Juso Dedic ,  Saul Darzy ,  Gavin Lambertus Allen

    IPC: H03M1/12 ,  H03M1/66

    CPC classification number: H03M1/0624 ,  H03M1/12 ,  H03M1/747

    Abstract: Mixed-signal circuitry, comprising: a first switching-circuitry unit for use in an analog-to-digital converter; and a second switching-circuitry unit for use in a digital-to-analog converter, wherein: the first switching-circuitry unit is configured to sample an input analog signal and output a plurality of samples based on a first plurality of clock signals; the second switching-circuitry unit is configured to generate an output analog signal based on a plurality of data signals and a second plurality of clock signals; and the first and second pluralities of dock signals have the same specifications as one another.

    Abstract translation: 混合信号电路，包括：用于模数转换器的第一开关电路单元; 以及用于数模转换器的第二开关电路单元，其中：所述第一开关电路单元被配置为对输入的模拟信号进行采样，并且基于第一多个时钟信号输出多个采样; 第二开关电路单元被配置为基于多个数据信号和第二多个时钟信号产生输出模拟信号; 并且第一和第二多个码头信号具有彼此相同的规格。

    Circuitry and methods for use in mixed-signal circuitry
    5.
    发明授权
    Circuitry and methods for use in mixed-signal circuitry 有权
    用于混合信号电路的电路和方法

    公开(公告)号：US09054722B2

    公开(公告)日：2015-06-09

    申请号：US14025330

    申请日：2013-09-12

    Applicant: Fujitsu Semiconductor Limited

    Inventor： Ian Juso Dedic ,  Saul Darzy ,  Gavin Lambertus Allen

    IPC: H03M1/10

    CPC classification number: H03M1/1009 ,  H03M1/10 ,  H03M1/745

    Abstract: A method of calibrating switching circuitry, the switching circuitry comprising a measurement node and a plurality of output switches connected to the measurement node, and the circuitry being configured, in each clock cycle of a series of clock cycles, to control whether or not one or more of said output switches carry a given current based upon input data, the method comprising: inputting a plurality of different data sequences to the circuitry, each sequence causing a given pattern of voltages to occur at the measurement node as a result of currents passing through the output switches; measuring the voltages occurring at the measurement node for each said sequence; and calibrating the switching circuitry in dependence upon a result of said measuring.

    Abstract translation: 一种校准开关电路的方法，所述开关电路包括连接到所述测量节点的测量节点和多个输出开关，并且所述电路在一系列时钟周期的每个时钟周期中被配置以控制是否一个或者 更多的所述输出开关基于输入数据携带给定的电流，该方法包括：向电路输入多个不同的数据序列，每个序列导致给定的电压模式由于电流通过而在测量节点处出现 输出开关; 测量每个所述序列在测量节点处出现的电压; 并根据所述测量的结果校准开关电路。

    Low-noise flip-chip packages and flip chips thereof
    6.
    发明授权
    Low-noise flip-chip packages and flip chips thereof 有权
    低噪声倒装芯片封装和倒装芯片

    公开(公告)号：US09136238B2

    公开(公告)日：2015-09-15

    申请号：US14152609

    申请日：2014-01-10

    Applicant: FUJITSU SEMICONDUCTOR LIMITED

    Inventor： Ian Juso Dedic ,  Ghazanfer Ali

    IPC: H01L23/12 ,  H01L23/00 ,  H01L23/498 ,  H01L23/50 ,  H01L23/552

    CPC classification number: H01L24/17 ,  H01L23/12 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/14 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

    Abstract: A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.

    Abstract translation: 一种低噪声倒装芯片封装，包括：具有第一和第二相对主面的载体基板; 以及经由连接阵列以面朝下的方式连接到所述载体基板的所述第一主面上的倒装芯片基板，其中：所述倒装芯片基板至少包括彼此间隔开的第一和第二电路部分; 倒装芯片基板包括位于第一和第二电路部分之间的基板接触边界; 并且第一电路部分，第二电路部分和衬底接触边界中的每一个具有其自己的单独的信号参考连接，其经由穿过载体衬底的连接阵列的相应连接延伸到在第二主面处的相应电接触 用于连接到外部电路中的公共信号参考元件的载体衬底。

    LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF
    7.
    发明申请
    LOW-NOISE FLIP-CHIP PACKAGES AND FLIP CHIPS THEREOF 有权
    低噪音片式包装及其盖子

    公开(公告)号：US20140124930A1

    公开(公告)日：2014-05-08

    申请号：US14152609

    申请日：2014-01-10

    Applicant: FUJITSU SEMICONDUCTOR LIMITED

    Inventor： Ian Juso Dedic ,  Ghazanfer Ali

    IPC: H01L23/00

    CPC classification number: H01L24/17 ,  H01L23/12 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/14 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

    Abstract: A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.

    Abstract translation: 一种低噪声倒装芯片封装，包括：具有第一和第二相对主面的载体基板; 以及经由连接阵列以面朝下的方式连接到所述载体基板的所述第一主面上的倒装芯片基板，其中：所述倒装芯片基板至少包括彼此间隔开的第一和第二电路部分; 倒装芯片基板包括位于第一和第二电路部分之间的基板接触边界; 并且第一电路部分，第二电路部分和衬底接触边界中的每一个具有其自己的单独的信号参考连接，其经由穿过载体衬底的连接阵列的相应连接延伸到在第二主面处的相应电接触 用于连接到外部电路中的公共信号参考元件的载体衬底。

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