公开(公告)号：US20160328511A1

公开(公告)日：2016-11-10

申请号：US14704488

申请日：2015-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: G06F17/50 ,  H01L23/522

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

Abstract translation: 公开了在IC设计的布局中所选择的区域（例如，包括关键区域）的识别和部分重新路由的方法以及所得到的设备。 实施例包括将IC器件的设计数据与制造IC器件的制造工艺标准进行比较; 在设计数据中，至少部分地基于所述布局区域中的金属段，互连段或其组合的接近来识别布局区域; 在所述布局区域中执行部分重路由以基本上满足所述准则，其中至少一个互连元件被移位或扩展; 并将部分重新路由集成到用于制造过程中的设计数据中。

公开(公告)号：US20150380246A1

公开(公告)日：2015-12-31

申请号：US14315659

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiang HU ,  Yuping REN ,  Duohui BEI ,  Sipeng GU ,  Huang LIU

IPC: H01L21/033 ,  H01L21/311 ,  H01L23/538

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.

Abstract translation: 提供了用于在电路结构上的尺寸控制的通孔形成的方法，包括在多个相邻的导电结构上。 所述方法包括例如在电路结构之上提供图案化的多层堆叠结构，所述堆叠结构包括至少一层，以及在所述至少一层上方的图案转移层，所述图案转移层被图案化 至少有一个通孔; 在所述至少一个通孔开口内提供侧壁间隔层，以形成至少一个尺寸控制的通孔开口; 以及使用所述至少一个尺寸控制的通孔开口蚀刻穿过所述堆叠结构的所述至少一个层，以便于在所述电路结构上提供通孔。 在一个实施方案中，堆叠结构包括设置在电介质层和平坦化层之间的图案化硬掩模层内的沟槽开口，并且通孔部分地自对准沟槽。

公开(公告)号：US20200235002A1

公开(公告)日：2020-07-23

申请号：US16252114

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haigou HUANG ,  Yuping REN ,  Paul ACKMANN ,  Guoxiang NING

IPC: H01L21/768 ,  H01L21/027 ,  H01L21/283 ,  H01L21/311

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to gap fill void and connection structures and methods of manufacture. The structure includes: a gate structure comprising source and drain regions; a gate contact in direct contact and overlapping the gate structure; and source and drain contacts directly connecting to the source and drain regions, respectively.

公开(公告)号：US20170186687A1

公开(公告)日：2017-06-29

申请号：US15458140

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guoxiang NING ,  Yuping REN ,  Chin Teong LIM ,  Xusheng WU ,  Paul ACKMANN

IPC: H01L23/522 ,  G06F17/50 ,  H01L23/528 ,  G03F1/36

CPC classification number: H01L23/5226 ,  G03F1/36 ,  G06F17/5077 ,  G06F17/5081 ,  G06F2217/12 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207

Abstract: Methods for identification and partial re-routing of selected areas (e.g., including critical areas) in a layout of an IC design and the resulting device are disclosed. Embodiments include comparing design data of an IC device against criteria of manufacturing processes to manufacture the IC device; identifying in the design data a layout area based, at least in part, on proximity of metal segments, interconnecting segments, or a combination thereof in the layout area; performing partial re-routing in the layout area to substantially meet the criteria, wherein at least one interconnecting element is shifted or extended; and integrating the partial re-routing into the design data for use in the manufacturing processes.

公开(公告)号：US20170061044A1

公开(公告)日：2017-03-02

申请号：US14841037

申请日：2015-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guo Xiang NING ,  Yuping REN ,  David POWER ,  Lalit SHOKEEN ,  Chin Teong LIM ,  Paul W. ACKMANN ,  Xiang HU

IPC: G06F17/50 ,  G03F1/36 ,  G05B15/02

CPC classification number: G06F17/5009 ,  G03F1/36 ,  G06F17/5081

Abstract: A method and apparatus for generating a final dielectric etch compensation table and a final hard mask etch compensation table for either OPC or MPC process flows are provided. Embodiments include performing an overlap pattern classification on a wafer; calibrating a dielectric etch bias or a hard mask etch bias based on the pattern classification; comparing either a CD overlap of a via layer with a metal layer and a CD overlap of the via layer with a lower connecting metal layer or a CD overlap of the metal layer with an upper connecting via layer and a CD overlap of the metal layer with the via layer against a criteria; outputting final dielectric etch compensation and hard mask etch compensation tables to either OPC or MPC process flows; and repeating the steps of calibrating, comparing, and outputting for either the via layer or metal layer remaining.

Abstract translation: 提供了用于产生用于OPC或MPC工艺流程的最终电介质蚀刻补偿表和最终硬掩模蚀刻补偿表的方法和装置。 实施例包括在晶片上执行重叠图案分类; 基于图案分类来校准电介质蚀刻偏压或硬掩模蚀刻偏压; 将通孔层与金属层的CD重叠与通孔层的CD重叠与金属层的下连接金属层或CD重叠与上连接通孔层和金属层的CD重叠与 通过层反对标准; 将最终介电蚀刻补偿和硬掩模蚀刻补偿表输出到OPC或MPC工艺流程; 并重复校准，比较和输出剩余的通孔层或金属层的步骤。

公开(公告)号：US20160099171A1

公开(公告)日：2016-04-07

申请号：US14969154

申请日：2015-12-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiang HU ,  Yuping REN ,  Duohui BEI ,  Sipeng GU ,  Huang LIU

IPC: H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76816 ,  H01L21/02063 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods are provided for dimension-controlled via formation over a circuit structure, including over multiple adjacent conductive structures. The method(s) includes, for instance, providing a patterned multi-layer stack structure above the circuit structure, the stack structure including at least one layer, and a pattern transfer layer above the at least one layer, the pattern transfer layer being patterned with at least one via opening; providing a sidewall spacer layer within the at least one via opening to form at least one dimension-controlled via opening; and etching through the at least one layer of the stack structure using the at least one dimension-controlled via opening to facilitate providing the via(s) over the circuit structure. In one implementation, the stack structure includes a trench-opening within a patterned hard mask layer disposed between a dielectric layer and a planarization layer, and the via(s) is partially self-aligned to the trench.