公开(公告)号：US10020260B1

公开(公告)日：2018-07-10

申请号：US15388530

申请日：2016-12-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： Shafaat Ahmed ,  Benjamin G. Moser ,  Vimal Kumar Kamineni ,  Dinesh Koli ,  Vishal Chhabra

IPC: H01L23/48 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/265 ,  H01L21/321 ,  H01L21/3213 ,  H01L23/522

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a corrosion and/or etch protection layer for contacts and interconnect metallization integration structures and methods of manufacture. The structure includes a metallization structure formed within a trench of a substrate and a layer of cobalt phosphorous (CoP) on the metallization structure. The CoP layer is structured to prevent metal migration from the metallization structure and corrosion of the metallization structure during etching processes.

公开(公告)号：US09917009B2

公开(公告)日：2018-03-13

申请号：US15228317

申请日：2016-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L21/76 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423 ,  H01L23/522 ,  H01L23/532 ,  H01L29/66 ,  H01L21/306

CPC classification number: H01L21/76898 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/66666

Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.

公开(公告)号：US10446443B2

公开(公告)日：2019-10-15

申请号：US15877549

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L29/66 ,  H01L21/768 ,  H01L21/306 ,  H01L23/532 ,  H01L29/423 ,  H01L29/417 ,  H01L23/485 ,  H01L23/522

Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.

公开(公告)号：US10043708B2

公开(公告)日：2018-08-07

申请号：US15347119

申请日：2016-11-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Viraj Sardesai ,  Suraj K. Patil ,  Scott Beasor ,  Vimal Kumar Kamineni

IPC: H01L29/40 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

Abstract: A process for forming a conductive structure includes the formation of a self-aligned silicide cap over a cobalt-based contact. The silicide cap is formed in situ by the deposition of a thin silicon layer over exposed portions of a cobalt contact, followed by heat treatment to react the deposited silicon with the cobalt and form cobalt silicide, which is an effective barrier to cobalt migration and oxidation.

公开(公告)号：US20180158733A1

公开(公告)日：2018-06-07

申请号：US15877549

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L21/768 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L21/306 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L21/30625 ,  H01L21/76816 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/66666

Abstract: An integrated circuit product includes a substrate, an interlayer dielectric (ILD) material positioned above the substrate and a through-substrate-via (TSV) extending continuously through the substrate and the ILD material. The TSV includes a substrate portion of the TSV that is positioned in and extends continuously through the substrate and an ILD portion of the TSV that is positioned in and extends continuously through the ILD. An insulating liner layer is selectively positioned between and separates the substrate portion of the TSV and the substrate, wherein the selectively positioned insulating liner layer does not extend from the substrate to the ILD material.

公开(公告)号：US20180040511A1

公开(公告)日：2018-02-08

申请号：US15228317

申请日：2016-08-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Himani Suhag Kamineni ,  Vimal Kumar Kamineni ,  Daniel Smith ,  Maxwell Lippitt

IPC: H01L21/768 ,  H01L29/423 ,  H01L21/306 ,  H01L23/532 ,  H01L29/66 ,  H01L29/417 ,  H01L23/522

CPC classification number: H01L21/76898 ,  H01L21/30625 ,  H01L23/481 ,  H01L23/485 ,  H01L23/5226 ,  H01L23/53209 ,  H01L23/53214 ,  H01L23/53223 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L29/41741 ,  H01L29/4232 ,  H01L29/66666

Abstract: One illustrative method disclosed includes, among other things, forming a semiconductor device above a semiconducting substrate, forming a device level contact to the semiconductor device and, after forming the device level contact, performing at least one common process operation so as to form a through-substrate-via (TSV) in a trench in the substrate, a TSV contact structure that is conductively coupled to the TSV and a conductive metallization element that is conductively coupled to the device level contact.