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6 条记录 (耗时 0.015 秒)

    PROGRAMMABLE ACTIVE COOLING DEVICE
    4.
    发明申请
    PROGRAMMABLE ACTIVE COOLING DEVICE 有权
    可编程主动冷却装置

    公开(公告)号：US20160293515A1

    公开(公告)日：2016-10-06

    申请号：US14673843

    申请日：2015-03-30

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Kheng Chok TEE ,  Juan Boon TAN ,  Wei LIU ,  Kam Chew LEONG

    IPC分类号： H01L23/38 ,  H01L21/265

    CPC分类号： H01L23/3677 ,  H01L21/7624 ,  H01L23/367 ,  H01L23/3736 ,  H01L23/3738 ,  H01L23/38 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1218 ,  H01L29/66772 ,  H01L29/78603 ,  H01L35/30 ,  H01L35/32

    摘要： Cooling devices for SOI wafers and methods for forming the devices are presented. A substrate having a top surface layer, a support substrate and an insulator layer isolating the top surface layer from the support substrate is provided. At least one device is disposed in the top surface layer of the substrate. The IC includes a cooling device. The cooling device includes a doped layer which is disposed in a top surface of the support substrate, and a RDL layer disposed within the support substrate below the doped layer for providing connections to hotspots in the doped layer to facilitate thermoelectric conduction of heat in the hotspots away from the hotspots.

    摘要翻译： 介绍了用于SOI晶片的冷却装置及其形成方法。 提供了具有顶表面层，支撑衬底和将顶表面层与支撑衬底隔离的绝缘体层的衬底。 至少一个器件设置在衬底的顶表面层中。 IC包括冷却装置。 冷却装置包括设置在支撑衬底的顶表面中的掺杂层和设置在掺杂层下方的支撑衬底内的RDL层，用于提供与掺杂层中的热点的连接，以便于热点热电传导 远离热点。

    TSV WITHOUT ZERO ALIGNMENT MARKS
    5.
    发明申请
    TSV WITHOUT ZERO ALIGNMENT MARKS 有权
    TSV没有零对齐标志

    公开(公告)号：US20150170994A1

    公开(公告)日：2015-06-18

    申请号：US14106870

    申请日：2013-12-16

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Shunqiang GONG ,  Juan Boon TAN ,  Wei LIU ,  Hai CONG

    IPC分类号： H01L23/48 ,  H01L23/544 ,  H01L21/768

    CPC分类号： H01L23/544 ,  H01L21/76816 ,  H01L21/76898 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor device and method of forming a semiconductor device are disclosed. The method includes providing a substrate. A dielectric layer is formed on the substrate. The dielectric layer includes an upper and lower level. The upper level of the dielectric layer is patterned to form at least first and second trench openings and alignment mark openings. One of the first and second trench openings serve as a through via (TV) trench while another trench opening serves as an interconnect trench. A TV opening aligned to the TV trench is formed. The TV opening extends partially into the substrate. A conductive layer is formed over the substrate to fill the trenches and the openings.

    摘要翻译： 公开了形成半导体器件的半导体器件和方法。 该方法包括提供基板。 在基板上形成电介质层。 电介质层包括上层和下层。 图案化电介质层的上层以形成至少第一和第二沟槽开口和对准标记开口。 第一和第二沟槽开口中的一个用作通孔（TV）沟槽，而另一个沟槽开口用作互连沟槽。 形成了与电视槽对准的电视开口。 TV开口部分地延伸到基板中。 导电层形成在衬底上以填充沟槽和开口。

    NON-VOLATILE MEMORY DEVICE WITH TSI/TSV APPLICATION
    6.
    发明申请
    NON-VOLATILE MEMORY DEVICE WITH TSI/TSV APPLICATION 有权
    具有TSI / TSV应用的非易失性存储器件

    公开(公告)号：US20140264235A1

    公开(公告)日：2014-09-18

    申请号：US13906289

    申请日：2013-05-30

    申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

    发明人： Shunqiang GONG ,  Juan Boon TAN ,  Lei WANG ,  Wei LIU ,  Wanbing YI ,  Jens OSWALD

    IPC分类号： H01L23/538 ,  H01L27/22 ,  H01L27/24

    CPC分类号： H01L23/5386 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L27/222 ,  H01L27/2463 ,  H01L2224/16225 ,  H01L2924/15311

    摘要： Memory devices and methods for forming the device are disclosed. The device includes a substrate having an array surface and a non-array surface and a memory array having a plurality of memory cells interconnected by first conductors in a first direction and second conductors in a second direction. The memory array is disposed on the array surface of the substrate. The device further includes through silicon via (TSV) contacts disposed in the substrate. The TSV contacts extend from the array surface to the non-array surface, enabling electrical connections to the array from the non-array surface.

    摘要翻译： 公开了用于形成装置的存储装置和方法。 该器件包括具有阵列表面和非阵列表面的衬底和存储器阵列，该存储器阵列具有多个存储器单元，该多个存储器单元通过第一方向的第一导体和第二方向上的第二导体互连。 存储器阵列设置在衬底的阵列表面上。 该器件还包括通过布置在衬底中的硅通孔（TSV）触点。 TSV触点从阵列表面延伸到非阵列表面，使得能够从非阵列表面到阵列的电连接。