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公开(公告)号：US20120159057A1
公开(公告)日：2012-06-21
申请号：US12970890
申请日：2010-12-16
IPC分类号： G06F13/00
CPC分类号： G06F12/00 , G06F13/1605 , Y02D10/14
摘要： Techniques are described for controlling availability of memory. As memory write operations are processed, the contents of memory targeted by the write operations are read and compared to the data to be written. The availability of the memory for subsequent write operations is controlled based on the outcomes of the comparing. How many concurrent write operations are being executed may vary according to the comparing. In one implementation, a pool of tokens is maintained based on the comparing. The tokens represent units of power. When write operations require more power, for example when they will alter the values of more cells in PCM memory, they draw (and eventually return) more tokens. The token pool can act as a memory-availability mechanism in that tokens must be obtained for a write operation to be executed. When and how many tokens are reserved or recycled can vary according to implementation.
摘要翻译： 描述了用于控制存储器可用性的技术。 当处理存储器写入操作时，写入操作所针对的存储器的内容被读取并与要写入的数据进行比较。 基于比较的结果来控制用于后续写入操作的存储器的可用性。 正在执行的并发写操作有多少可能会根据比较而有所不同。 在一个实现中，基于比较来维护令牌池。 代币代表权力单位。 当写操作需要更多的功率时，例如当它们将改变PCM存储器中更多单元的值时，它们绘制（并最终返回）更多的令牌。 令牌池可以充当内存可用性机制，因为必须获得令牌才能执行写操作。 保留或回收的代码何时以及有多少可以根据实现而有所不同。
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公开(公告)号：US09753858B2
公开(公告)日：2017-09-05
申请号：US13307776
申请日：2011-11-30
申请人： Gabriel H. Loh , Mark D. Hill
发明人： Gabriel H. Loh , Mark D. Hill
IPC分类号： G06F12/00 , G06F12/0893 , G06F12/0864 , G06F12/123 , G06F12/0879 , G06F12/0831
CPC分类号： G06F12/0893 , G06F12/0831 , G06F12/0864 , G06F12/0879 , G06F12/123 , Y02D10/13
摘要： A system and method for efficient cache data access in a large row-based memory of a computing system. A computing system includes a processing unit and an integrated three-dimensional (3D) dynamic random access memory (DRAM). The processing unit uses the 3D DRAM as a cache. Each row of the multiple rows in the memory array banks of the 3D DRAM stores at least multiple cache tags and multiple corresponding cache lines indicated by the multiple cache tags. In response to receiving a memory request from the processing unit, the 3D DRAM performs a memory access according to the received memory request on a given cache line indicated by a cache tag within the received memory request. Rather than utilizing multiple DRAM transactions, a single, complex DRAM transaction may be used to reduce latency and power consumption.
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公开(公告)号：US09331053B2
公开(公告)日：2016-05-03
申请号：US14016063
申请日：2013-08-31
IPC分类号： H01L21/00 , H01L25/065 , H01L23/00 , H01L23/427
CPC分类号： H01L25/0657 , H01L23/427 , H01L24/01 , H01L24/05 , H01L24/08 , H01L24/80 , H01L2224/0557 , H01L2224/05571 , H01L2224/08146 , H01L2224/16227 , H01L2225/06541 , H01L2225/06589 , H01L2924/01322 , H01L2924/12042 , H01L2924/00 , H01L2924/00012
摘要： Various stacked semiconductor chip arrangements and methods of manufacturing the same are disclosed. In one aspect, an apparatus is provided that includes a first semiconductor chip, a second semiconductor chip mounted on the first semiconductor chip, and a first portion of a phase change material positioned in a first pocket associated with the first semiconductor chip or the second semiconductor chip to store heat generated by one or both of the first and second semiconductor chips.
摘要翻译： 公开了各种叠层半导体芯片布置及其制造方法。 一方面，提供了一种装置，其包括第一半导体芯片，安装在第一半导体芯片上的第二半导体芯片和位于与第一半导体芯片或第二半导体芯片相关联的第一凹槽中的相变材料的第一部分 芯片以存储由第一和第二半导体芯片中的一个或两个产生的热量。
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公开(公告)号：US09146846B2
公开(公告)日：2015-09-29
申请号：US13617673
申请日：2012-09-14
CPC分类号： G06F12/00 , G06F12/0207 , G06F12/0653 , G06F2212/1016
摘要： A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
摘要翻译： 存储器实现可编程物理地址映射，可以改变以反映对存储器的观察或预期的改变的存储器访问模式。 存储器采用地址解码逻辑，其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。 物理地址映射可以将数据定位在存储器的一个或多个存储体和行中，以便于给定访问模式更有效的存储器访问。 存储器的硬件采用的可编程物理地址映射可以包括但不限于硬连线逻辑门，可编程查找表或其它映射表，可重构逻辑或其组合。 物理地址映射可以针对整个存储器或基于每存储器区域编程。
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公开(公告)号：US08868843B2
公开(公告)日：2014-10-21
申请号：US13307815
申请日：2011-11-30
申请人： Gabriel H. Loh , Mark D. Hill
发明人： Gabriel H. Loh , Mark D. Hill
IPC分类号： G06F12/08
CPC分类号： G06F12/0888 , G06F12/0893 , Y02D10/13
摘要： A system and method for efficiently determining whether a requested memory location is in a large row-based memory of a computing system. A computing system includes a processing unit that generates memory requests on a first chip and a cache (LLC) on a second chip connected to the first chip. The processing unit includes an access filter that determines whether to access the cache. The cache is fabricated on top of the processing unit. The processing unit determines whether to access the access filter for a given memory request. The processing unit accesses the access filter to determine whether given data associated with a given memory request is stored within the cache. In response to determining the access filter indicates the given data is not stored within the cache, the processing unit generates a memory request to send to off-package memory.
摘要翻译： 一种用于有效地确定所请求的存储器位置是否在计算系统的大型基于行的存储器中的系统和方法。 计算系统包括处理单元，其在与第一芯片连接的第二芯片上的第一芯片上生成存储器请求和高速缓存（LLC）。 处理单元包括确定是否访问高速缓存的访问过滤器。 高速缓存是在处理单元之上制造的。 处理单元确定是否访问给定存储器请求的访问过滤器。 处理单元访问访问过滤器以确定与给定存储器请求相关联的给定数据是否存储在高速缓存中。 响应于确定访问过滤器指示给定数据未被存储在高速缓存中，处理单元产生存储器请求以发送到脱机存储器。
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公开(公告)号：US07692946B2
公开(公告)日：2010-04-06
申请号：US11771054
申请日：2007-06-29
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译： 对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。 第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。 还公开了其他实施例。
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公开(公告)号：US09135185B2
公开(公告)日：2015-09-15
申请号：US13726143
申请日：2012-12-23
申请人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
发明人： Gabriel H. Loh , Bradford M. Beckmann , James M. O'Connor , Michael Ignatowski , Michael J. Schulte , Lisa R. Hsu , Nuwan S. Jayasena
CPC分类号： G06F12/1027 , H01L25/18 , H01L2224/16225 , H01L2225/06565 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
摘要翻译： 芯片堆叠存储器件在器件的一个或多个逻辑管芯上并入数据转换控制器，以提供数据转换服务，用于存储在芯片堆叠存储器件中或从芯片堆叠的存储器件中取出的数据。 由数据转换控制器实现的数据转换操作可以包括压缩/解压缩操作，加密/解密操作，格式转换，磨损均衡转换，数据排序操作等。 由于逻辑管芯和存储器管芯的紧密集成，与堆叠式存储器件外部的器件执行的操作相比，数据转换控制器可以执行具有更高带宽和更低延迟和功耗的数据转换操作。
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公开(公告)号：US08775762B2
公开(公告)日：2014-07-08
申请号：US13465153
申请日：2012-05-07
CPC分类号： G06F13/1642
摘要： A memory controller includes a batch unit, a batch scheduler, and a memory command scheduler. The batch unit includes a plurality of source queues for receiving memory requests from a plurality of sources. Each source is associated with a selected one of the source queues. The batch unit is operable to generate batches of memory requests in the source queues. The batch scheduler is operable to select a batch from one of the source queues. The memory command scheduler is operable to receive the selected batch from the batch scheduler and issue the memory requests in the selected batch to a memory interfacing with the memory controller.
摘要翻译： 存储器控制器包括批量单元，批量调度器和存储器命令调度器。 批量单元包括用于从多个源接收存储器请求的多个源队列。 每个源与选定的一个源队列相关联。 批处理单元可操作以在源队列中生成批次的存储器请求。 批处理调度器可操作以从源队列中的一个队列中选择一批。 存储器命令调度器可操作以从批处理调度器接收所选批次，并将所选批次中的存储器请求发送到与存储器控制器接口的存储器。
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公开(公告)号：US20140108885A1
公开(公告)日：2014-04-17
申请号：US13649745
申请日：2012-10-11
申请人： Gabriel H. Loh , Vilas K. Sridharan
发明人： Gabriel H. Loh , Vilas K. Sridharan
CPC分类号： G06F11/1044
摘要： An integrated circuit includes a memory having an address space and a memory controller coupled to the memory for accessing the address space in response to received memory accesses. The memory controller further accesses a plurality of data elements in a first portion of the address space, and reliability data corresponding to the plurality of data elements in a second portion of the address space.
摘要翻译： 集成电路包括具有地址空间的存储器和耦合到存储器的存储器控制器，用于响应于接收到的存储器访问来访问地址空间。 存储器控制器还访问地址空间的第一部分中的多个数据元素以及与地址空间的第二部分中的多个数据元素相对应的可靠性数据。
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公开(公告)号：US20140082322A1
公开(公告)日：2014-03-20
申请号：US13617673
申请日：2012-09-14
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F12/0207 , G06F12/0653 , G06F2212/1016
摘要： A memory implements a programmable physical address mapping that can change to reflect changing memory access patterns, observed or anticipated, to the memory. The memory employs address decode logic that can implement any of a variety of physical address mappings between physical addresses and corresponding memory locations. The physical address mappings may locate the data within one or more banks and rows of the memory so as to facilitate more efficient memory accesses for a given access pattern. The programmable physical address mapping employed by the hardware of the memory can include, but is not limited to, hardwired logic gates, programmable look-up tables or other mapping tables, reconfigurable logic, or combinations thereof. The physical address mapping may be programmed for the entire memory or on a per-memory region basis.
摘要翻译： 存储器实现可编程物理地址映射，可以改变以反映对存储器的观察或预期的改变的存储器访问模式。 存储器采用地址解码逻辑，其可以实现物理地址和相应存储器位置之间的各种物理地址映射中的任何一种。 物理地址映射可以将数据定位在存储器的一个或多个存储体和行中，以便于给定访问模式更有效的存储器访问。 存储器的硬件采用的可编程物理地址映射可以包括但不限于硬连线逻辑门，可编程查找表或其它映射表，可重构逻辑或其组合。 物理地址映射可以针对整个存储器或基于每存储器区域编程。
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