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    Method and apparatus for a unified parallel processing architecture
    5.
    发明授权
    Method and apparatus for a unified parallel processing architecture 失效
    统一并行处理架构的方法和装置

    公开(公告)号：US5428803A

    公开(公告)日：1995-06-27

    申请号：US912964

    申请日：1992-07-10

    申请人： Steve S. Chen ,  Douglas R. Beard ,  George A. Spix ,  Edward C. Priest ,  John M. Wastlick ,  James M. VanDyke

    发明人： Steve S. Chen ,  Douglas R. Beard ,  George A. Spix ,  Edward C. Priest ,  John M. Wastlick ,  James M. VanDyke

    IPC分类号： G06F9/38 ,  G06F1/10 ,  G06F12/06 ,  G06F13/16 ,  G06F15/173 ,  G06F3/60

    CPC分类号： G06F13/1657 ,  G06F1/10 ,  G06F13/1663 ,  G06F15/17337 ,  G06F15/17381

    摘要： A unified parallel processing architecture connects together an extendible number of clusters of multiple numbers of processors to create a high performance parallel processing computer system. Multiple processors are grouped together into four or more physically separable clusters, each cluster having a common cluster shared memory that is symmetrically accessible by all of the processors in that cluster; however, only some of the clusters are adjacently interconnected. Clusters are adjacently interconnected to form a floating shared memory if certain memory access conditions relating to relative memory latency and relative data locality can create an effective shared memory parallel programming environment. A shared memory model can be used with programs that can be executed in the cluster shared memory of a single cluster, or in the floating shared memory that is defined across an extended shared memory space comprised of the cluster shared memories of any set of adjacently interconnected clusters. A distributed memory model can be used with any programs that are to be executed in the cluster shared memories of any non-adjacently interconnected clusters. The adjacent interconnection of multiple clusters of processors to a create a floating shared memory effectively combines all three type of memory models, pure shared memory, extended shared memory and distributed shared memory, into a unified parallel processing architecture.

    摘要翻译： 统一的并行处理架构将多个处理器的可扩展数量的集群连接在一起，以创建高性能并行处理计算机系统。 多个处理器被分组到四个或更多个物理上可分离的群集中，每个群集具有由该群集中的所有处理器对称地访问的公共群集共享存储器; 然而，只有一些集群是相互关联的。 如果与相对存储器延迟和相对数据局部性相关的某些存储器访问条件可以创建有效的共享存储器并行编程环境，则群集相互互连以形成浮动共享存储器。 共享存储器模型可以与可以在单个集群的集群共享存储器中执行的程序一起使用，或者在由包括相邻互连的任何集合的集群共享存储器的扩展共享存储器空间中定义的浮动共享存储器中使用 集群。 分布式存储器模型可以与要在任何非相邻互连的集群的集群共享存储器中执行的任何程序一起使用。 处理器的多个集群的相邻互连以创建浮动共享存储器有效地将所有三种类型的存储器模型，纯共享存储器，扩展共享存储器和分布式共享存储器组合成统一的并行处理架构。

    Method and apparatus for non-sequential resource access
    7.
    发明授权
    Method and apparatus for non-sequential resource access 失效
    用于非顺序资源访问的方法和装置

    公开(公告)号：US5208914A

    公开(公告)日：1993-05-04

    申请号：US535786

    申请日：1990-06-11

    申请人： Jimmie R. Wilson ,  Douglas R. Beard ,  Steve S. Chen ,  Roger E. Eckert ,  Richard E. Hessel ,  Andrew E. Phelps ,  Alexander A. Silbey ,  Brian D. Vanderwarn

    发明人： Jimmie R. Wilson ,  Douglas R. Beard ,  Steve S. Chen ,  Roger E. Eckert ,  Richard E. Hessel ,  Andrew E. Phelps ,  Alexander A. Silbey ,  Brian D. Vanderwarn

    IPC分类号： G06F9/46 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F12/00 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F15/78 ,  G06F15/80

    CPC分类号： G06F15/17375 ,  G06F15/17381 ,  G06F15/8076 ,  G06F15/8092 ,  G06F8/433 ,  G06F8/45 ,  G06F9/30021 ,  G06F9/30094 ,  G06F9/3013 ,  G06F9/30141 ,  G06F9/30149 ,  G06F9/3802 ,  G06F9/3804 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857

    摘要： A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor. The switching logic for the requestor includes a tag queue for storing the request tags associated with the resource requests, logic means for associating the respective request tag from the tag queue with a resource response, and means for returning the resource response and respective request tag to the requestor. The switching logic associated with the shared resource includes switching means to route the request into and out of the shared resource, control logic to correctly route the request, logic to handle multiple decision requests, and logic to store or retrieve the ultimate data entity being requested.

    摘要翻译： 用于在多请求者系统中非顺序访问共享资源的方法和装置使用各种标签来有效地重新排序其目的地的数据。 以最简单的形式，标签将切换逻辑引导到缓冲器中的哪个位置，以定位用于方向信息的另一个标签，或者在缓冲器或处理器（寄存器）中放置与标签相关联的响应的位置。 例如，从存储器加载数据要求请求者提供请求信号，地址和请求标签。 请求信号验证地址和请求标签。 该地址指定所请求的数据在内存中的位置。 请求标签指定在将数据返回到处理器时放置数据的位置。 用于请求者的切换逻辑包括用于存储与资源请求相关联的请求标签的标记队列，用于将来自标签队列的相应请求标签与资源响应相关联的逻辑装置，以及用于将资源响应和相应请求标签返回到 请求者。 与共享资源相关联的切换逻辑包括将请求路由到共享资源和从共享资源引出的切换装置，控制逻辑以正确路由请求，处理多个决策请求的逻辑以及存储或检索被请求的最终数据实体的逻辑 。

    Flexible chaining in vector processor with selective use of vector registers as operand and result registers
    8.
    发明授权
    Flexible chaining in vector processor with selective use of vector registers as operand and result registers 失效
    矢量处理器的灵活链接，可选择性地使用向量寄存器作为操作数和结果寄存器

    公开(公告)号：US4661900A

    公开(公告)日：1987-04-28

    申请号：US858862

    申请日：1986-04-30

    申请人： Steve S. Chen ,  Alan J. Schiffleger

    发明人： Steve S. Chen ,  Alan J. Schiffleger

    IPC分类号： G06F9/30 ,  G06F9/38 ,  G06F13/18 ,  G06F15/17 ,  G06F15/78 ,  G06F15/347

    CPC分类号： G06F9/3004 ,  G06F13/18 ,  G06F15/17 ,  G06F15/8084 ,  G06F9/30087 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3885

    摘要： A pair of processors are each connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitate multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.

    摘要翻译： 一对处理器各自通过多个存储器参考端口连接到中央存储器。 处理器还进一步连接到多个共享寄存器，这些共享寄存器可以由任一处理器以与处理器内操作相称的速率直接寻址。 共享寄存器包括用于保存标量和地址信息的寄存器以及用于保存用于协调通过共享寄存器传送信息的信息的寄存器。 提供多端口存储器并且包括冲突解决电路，其感测并优先考虑对中央存储器的冲突引用。 每个CPU通过三个端口与中央存储器连接，每个端口处理可以进行的几种不同类型的存储器引用的不同的端口。 提供至少一个I / O端口以由处理器在中央存储器和外围存储设备之间传送信息时共享。 还公开了用于向量处理计算机中的矢量寄存器设计，并且提供每个寄存器由至少两个可独立寻址的存储器组成，以向功能单元传送数据或从功能单元接收数据。 多处理方法允许多处理器中的多任务处理，其中共享寄存器允许单个作业的不同作业或相关任务的独立任务并行运行，并且通过允许多个关键代码区域被独立同步来促进操作系统的多线程化 。

    Packaging architecture for a data server
    9.
    发明授权
    Packaging architecture for a data server 失效
    数据服务器的包装架构

    公开(公告)号：US5684671A

    公开(公告)日：1997-11-04

    申请号：US518003

    申请日：1995-08-22

    申请人： Forrest B. Hobbs ,  Richard G. Blewett ,  Scott A. Wentzka ,  Steve S. Chen ,  Kitrick B. Sheets ,  Sheldon D. Stevens

    发明人： Forrest B. Hobbs ,  Richard G. Blewett ,  Scott A. Wentzka ,  Steve S. Chen ,  Kitrick B. Sheets ,  Sheldon D. Stevens

    IPC分类号： G06F1/18 ,  G11B33/12 ,  H05K7/16 ,  H05K7/18 ,  G06F1/16 ,  H05K7/14

    CPC分类号： G11B33/128 ,  G06F1/183 ,  G06F1/184 ,  G06F1/187 ,  G06F1/188 ,  H05K7/1488

    摘要： A rack-mount data server includes a housing, a plurality of data server components supported by the housing, the components including at least one peripheral storage device, a logic chassis for the data server, at least one disk drive on which the data server stores files, and at least one power supply, and a plurality of racks coupled with the housing to accommodate the data server components, the racks including a first topmost rack accommodating the at least one peripheral storage device and a second rack accommodating the logic chassis, the housing supporting the second rack underneath the first rack as the second topmost rack. The data server also includes a front door and a top door, the top door and the front door being interlockable with each other such that when the top door and the front door are in their closed positions, one of the top door and the front door locks the other of the top door and the front door in its closed position. A security system monitors the closed and/or locked status of a number of components, including the front door.

    摘要翻译： 机架式数据服务器包括壳体，由壳体支撑的多个数据服务器组件，所述组件包括至少一个外围存储设备，用于数据服务器的逻辑机箱，数据服务器在其上存储的至少一个磁盘驱动器 文件和至少一个电源以及与外壳耦合以容纳数据服务器组件的多个机架，所述机架包括容纳至少一个外围存储设备的第一最顶端机架和容纳逻辑机箱的第二机架， 将第一机架下方的第二机架支撑为第二顶部机架。 数据服务器还包括前门和顶门，顶门和前门彼此互锁，使得当顶门和前门处于关闭位置时，顶门和前门之一 将顶门和前门中的另一个锁在其关闭位置。 安全系统监视包括前门在内的许多组件的关闭和/或锁定状态。