公开(公告)号：US07375564B2

公开(公告)日：2008-05-20

申请号：US10716146

申请日：2003-11-18

申请人： Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

发明人： Geun-Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/0818

摘要： A delay-locked loop includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes delay cells having various unit time delays. The number of delay cells is adjusted in response to a shift signal. The delay line receives the external clock signal and outputs an output clock signal. The filter unit generates the shift signal in response to the error control signal. In the delay-locked loop, the front delay cells, which compensate for a delay of an external clock signal having a high frequency, have short unit time delays. The rear delay cells, which compensate for a delay of the external clock signal having a low frequency, have long unit time delays.

摘要翻译： 延迟锁定环包括相位检测器，延迟线和滤波器单元。 相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较，并输出相位差作为误差控制信号。 延迟线包括具有各种单位时间延迟的延迟单元。 响应于移位信号调整延迟单元的数量。 延迟线接收外部时钟信号并输出​​输出时钟信号。 滤波器单元响应于误差控制信号产生移位信号。 在延迟锁定环路中，补偿具有高频率的外部时钟信号的延迟的前延迟单元具有较短的单位时间延迟。 补偿具有低频率的外部时钟信号的延迟的后延迟单元具有长的单位时间延迟。

公开(公告)号：US20080211554A1

公开(公告)日：2008-09-04

申请号：US12104997

申请日：2008-04-17

申请人： Geun Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

发明人： Geun Hee Cho ,  Byung-Hoon Jeong ,  Kyu-Hyoun Kim

IPC分类号： H03L7/06 ,  H03H11/26

CPC分类号： H03L7/0814 ,  H03K5/135 ,  H03K2005/00208 ,  H03L7/0818

摘要： A time delay compensation circuit comprises delay cells having various unit time delays. A delay-locked loop, a type of the time delay compensation circuit, includes a phase detector, a delay line, and a filter unit. The phase detector compares the phase of the external clock signal with that of the feedback clock signal and outputs a phase difference as an error control signal. The delay line includes a plurality of delay cells having various unit time delays. The number of delay cells is adjusted in response to a predetermined shift signal. The delay line receives the external clock signal and outputs an output clock signal, which is obtained by controlling the phase of the external clock signal. The filter unit generates the shift signal, which selects the number of delay cells in the delay line, in response to the error control signal. In the time delay compensation circuit, the front delay cells, which are used to compensate for a delay of an external clock signal having a high frequency, have short unit time delays so as to reduce jitter due to quantization error. Also, the rear delay cells, which are used to compensate for a delay of the external clock signal having a low frequency, have long unit time delays so as to reduce the number of delay cells required for the delay compensation.

摘要翻译： 时间延迟补偿电路包括具有各种单位时间延迟的延迟单元。 延迟锁定环路，延时补偿电路的一种类型，包括相位检测器，延迟线和滤波器单元。 相位检测器将外部时钟信号的相位与反馈时钟信号的相位进行比较，并输出相位差作为误差控制信号。 延迟线包括具有各种单位时间延迟的多个延迟单元。 响应于预定的移位信号来调整延迟单元的数量。 延迟线接收外部时钟信号并输出​​通过控制外部时钟信号的相位而获得的输出时钟信号。 滤波器单元响应于误差控制信号产生移位信号，该移位信号选择延迟线中的延迟单元的数量。 在延时补偿电路中，用于补偿具有高频率的外部时钟信号的延迟的前延迟单元具有短的单位时间延迟，以便减少由于量化误差引起的抖动。 此外，用于补偿具有低频率的外部时钟信号的延迟的后延迟单元具有长的单位时间延迟，以便减少延迟补偿所需的延迟单元的数量。

公开(公告)号：US08345501B2

公开(公告)日：2013-01-01

申请号：US13281762

申请日：2011-10-26

申请人： Byung-Hoon Jeong

发明人： Byung-Hoon Jeong

IPC分类号： G11C17/18 ,  G11C17/00 ,  G11C7/00

CPC分类号： G11C17/16 ,  G11C7/20 ,  G11C2029/0411

摘要： A semiconductor memory device and method of operating same are described. The semiconductor memory device includes a first anti-fuse array having a plurality of first anti-fuse elements that store first fuse data, a second anti-fuse array having a plurality of second anti-fuse elements that store error correction code (ECC) data associated with the first fuse data, and an ECC decoder configured to generate second fuse data by correcting the first fuse data using the ECC data.

摘要翻译： 描述半导体存储器件及其操作方法。 半导体存储器件包括具有存储第一熔丝数据的多个第一反熔丝元件的第一反熔丝阵列，具有存储纠错码（ECC）数据的多个第二反熔丝元件的第二反熔丝阵列 与ECC解码器配置成通过使用ECC数据校正第一熔丝数据来生成第二熔丝数据。

公开(公告)号：US07486577B2

公开(公告)日：2009-02-03

申请号：US11604700

申请日：2006-11-28

申请人： Hyung-Jik Kim ,  Byung-Hoon Jeong

发明人： Hyung-Jik Kim ,  Byung-Hoon Jeong

IPC分类号： G11C7/00

CPC分类号： G11C29/789 ,  G11C7/24

摘要： A repair circuit and related method of repair are disclosed. In the repair circuit, row repair or column repair control units are selectively actuated to perform respective repair functions within a semiconductor memory device in relation to a commonly provided defective address. Both post-package defects and/or before package defects may be repaired in response to the defective address.

摘要翻译： 公开了一种维修电路及相关的修理方法。 在维修电路中，行修复或列修复控制单元被选择性地启动，以相对于共同提供的缺陷地址在半导体存储器件内执行相应的修复功能。 两个后封装缺陷和/或在封装缺陷之前都可以针对缺陷地址进行修复。

公开(公告)号：US20050253631A1

公开(公告)日：2005-11-17

申请号：US11126428

申请日：2005-05-10

申请人： Chul-Soo Kim ,  Byung-Hoon Jeong

发明人： Chul-Soo Kim ,  Byung-Hoon Jeong

IPC分类号： G11C8/00 ,  G11C7/10 ,  H03L7/00 ,  H03L7/081

CPC分类号： H03L7/0812 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/222

摘要： We describe and claim an internal signal replication device and method. A circuit comprising a selector to select one of a plurality of internally generated clock signals, and a compensation circuit to replicate the selected clock signal from a reference clock signal.

摘要翻译： 我们描述并要求内部信号复制设备和方法。 一种电路，包括选择器以选择多个内部产生的时钟信号中的一个，以及补偿电路，以从参考时钟信号复制所选择的时钟信号。

公开(公告)号：US07979605B2

公开(公告)日：2011-07-12

申请号：US11742336

申请日：2007-04-30

申请人： Byung-Hoon Jeong ,  Hoe-Ju Chung

发明人： Byung-Hoon Jeong ,  Hoe-Ju Chung

IPC分类号： G06F3/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272

摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

摘要翻译： 等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。 寄存器单元可以包括n个寄存器。 值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。 寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。 延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。

公开(公告)号：US20080043547A1

公开(公告)日：2008-02-21

申请号：US11742336

申请日：2007-04-30

申请人： Byung-Hoon Jeong ,  Hoe-Ju Chung

发明人： Byung-Hoon Jeong ,  Hoe-Ju Chung

IPC分类号： G11C8/18 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2272

摘要： A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal.

摘要翻译： 等待时间控制电路包括FIFO控制器和寄存器单元。 FIFO控制器可以根据外部命令生成增加信号，并根据内部命令生成减少信号。 FIFO控制器还可以响应于增加信号和减小信号启用深度点信号。 寄存器单元可以包括n个寄存器。 值n（四舍五入）可以通过将最大数量的加性延迟和最大写入延迟数的较大值除以列周期延迟时间（tCCD）来获得。 寄存器可以响应于增加信号和时钟信号而存储与外部命令接收的地址，并且可以将地址或先前地址移位到相邻寄存器。 延迟控制电路将存储在寄存器中的地址作为与启用的深度点信号相对应的列地址。

公开(公告)号：US20070195638A1

公开(公告)日：2007-08-23

申请号：US11730793

申请日：2007-04-04

申请人： Byung-Hoon Jeong

发明人： Byung-Hoon Jeong

IPC分类号： G11C8/00

CPC分类号： G11C29/028 ,  G11C7/22 ,  G11C7/222 ,  G11C11/401 ,  G11C29/02 ,  G11C29/50012

摘要： A delay-locked loop (DLL) is disclosed with a phase detector configured to detect a phase difference between an external clock signal and an internal clock signal, a variable delay line configured to variably delay the external clock signal in relation to the phase difference to generate an intermediate clock signal, a selection unit configured to select between the intermediate clock signal and an inverted version of the intermediate clock signal in relation to an inversion control signal, and to generate an internal clock signal according to the selection, and an inversion determination unit configured to generate the inversion control signal in relation to transition of the external clock signal within a duty error margin.

摘要翻译： 延迟锁定环（DLL）被公开，相位检测器被配置为检测外部时钟信号和内部时钟信号之间的相位差，可变延迟线被配置为相对于相位差可变地延迟外部时钟信号 产生中间时钟信号，选择单元，被配置为在中间时钟信号和中间时钟信号的反相版本之间相对于反相控制信号进行选择，并根据该选择产生内部时钟信号，并且反演确定 被配置为在占空比误差容限内产生与外部时钟信号的转变相关的反相控制信号。

公开(公告)号：US20050281114A1

公开(公告)日：2005-12-22

申请号：US10951053

申请日：2004-09-27

申请人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

发明人： Hyung-Chan Choi ,  Chi-Wook Kim ,  Byung-Hoon Jeong

IPC分类号： G11C7/02 ,  G11C5/00 ,  G11C5/14 ,  G11C11/407

CPC分类号： G11C5/147 ,  G11C5/14

摘要： Decoupling capacitance of at least one shared capacitor is distributed among a plurality of voltage sources for enhanced performance with minimized area of a semiconductor device. The high nodes and the low nodes of such voltage sources each comprise at least two distinct nodes for lower noise at the voltage sources. The present invention is applied to particular advantage for coupling a variable number of shared capacitors to a data charge voltage source depending on a bit organization of the semiconductor device.

摘要翻译： 至少一个共享电容器的去耦电容分布在多个电压源之间，以便在半导体器件的面积最小的情况下提高性能。 这些电压源的高节点和低节点各自包括至少两个不同的节点，用于在电压源处降低噪声。 本发明应用于根据半导体器件的位组织将可变数量的共用电容器耦合到数据充电电压源的特别优点。

公开(公告)号：US20050248042A1

公开(公告)日：2005-11-10

申请号：US11121864

申请日：2005-05-04

申请人： Jong-Eon Lee ,  Chul-Soo Kim ,  Byung-Hoon Jeong ,  Jun-Hyung Kim ,  Young-Sun Min

发明人： Jong-Eon Lee ,  Chul-Soo Kim ,  Byung-Hoon Jeong ,  Jun-Hyung Kim ,  Young-Sun Min

IPC分类号： H01L21/8239 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10882

摘要： A semiconductor memory device having a memory cell array includes a plurality of first signal lines arranged on the memory cell array in the same direction and a plurality of second signal lines arranged on the memory cell array in a perpendicular direction to the first signal lines. The first signal lines are alternately arranged on at least two layers, and the second signal lines are arranged on a layer where the first signal lines are not arranged.

摘要翻译： 具有存储单元阵列的半导体存储器件包括沿着相同方向布置在存储单元阵列上的多个第一信号线和沿与第一信号线垂直的方向布置在存储单元阵列上的多个第二信号线。 第一信号线交替布置在至少两层上，并且第二信号线被布置在不布置第一信号线的层上。