公开(公告)号：US5746883A

公开(公告)日：1998-05-05

申请号：US723239

申请日：1996-09-27

申请人： Gi-ho Cha ,  Chi-jung Kang ,  Byung-hun Lee ,  Kyung-wook Lee

发明人： Gi-ho Cha ,  Chi-jung Kang ,  Byung-hun Lee ,  Kyung-wook Lee

IPC分类号： H01L21/02 ,  H01L21/00 ,  B32B31/00

CPC分类号： H01L21/67132

摘要： An apparatus for bonding semiconductor wafers firmly bonds the wafers to each other and can always lay the bonded wafers on a desired bonding plate. The bonding plates have a plurality of grooves formed on their respective surfaces to reduce the bond force between the wafers and the bonding plates of the apparatus, and to prevent the wafers from sliding off the plates due to an air cushion. An interval controlling pin projects from the surface of one of the bonding plates to reduce breakage of the wafers by maintaining an interval between the bonding plates as they are are rotated towards each other. An elastic pad portion is installed on one the bonding plates for providing an elastic force for the wafers placed on the bonding plates so that the wafers bond to each other properly when the bonding plates are further rotated towards each other.

摘要翻译： 用于接合半导体晶片的装置将晶片彼此牢固地结合，并且可以总是将结合的晶片放置在期望的接合板上。 接合板在它们各自的表面上形成有多个槽，以减少晶片和设备的接合板之间的结合力，并且防止晶片由于气垫而从板上脱落。 间隔控制销从一个接合板的表面突出，以通过在接合板之间彼此相对旋转时保持间隔而减小晶片的断裂。 弹性垫部分安装在一个粘合板上，用于为粘合板上放置的晶片提供弹性力，使得当粘结板进一步相互转动时，晶片彼此粘合。

公开(公告)号：US5665631A

公开(公告)日：1997-09-09

申请号：US563803

申请日：1995-11-28

申请人： Byoung-hun Lee ,  Chi-jung Kang ,  Kyung-wook Lee ,  Gi-ho Cha

发明人： Byoung-hun Lee ,  Chi-jung Kang ,  Kyung-wook Lee ,  Gi-ho Cha

IPC分类号： H01L21/304 ,  H01L21/02 ,  H01L21/18 ,  H01L21/20 ,  H01L27/12 ,  H01L21/76

CPC分类号： H01L21/76256 ,  Y10S438/938

摘要： A SOI substrate manufacturing method which corrects the warpage in the SOI substrate by varying the thickness of a semiconductor material layer additionally formed over the bonded combination of a semiconductor substrate and supporting substrate.

摘要翻译： 一种SOI衬底制造方法，其通过改变在半导体衬底和支撑衬底的接合组合上附加形成的半导体材料层的厚度来校正SOI衬底中的翘曲。

公开(公告)号：US20050145981A1

公开(公告)日：2005-07-07

申请号：US11072373

申请日：2005-03-04

申请人： Jong-hwan Kim ,  Gi-ho Cha ,  Mun-heui Choi ,  Chang-beom Jeong

发明人： Jong-hwan Kim ,  Gi-ho Cha ,  Mun-heui Choi ,  Chang-beom Jeong

IPC分类号： H01L29/73 ,  H01L21/84 ,  H01L27/12 ,  H01L21/336 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

公开(公告)号：US07582935B2

公开(公告)日：2009-09-01

申请号：US11072373

申请日：2005-03-04

申请人： Jong-hwan Kim ,  Gi-ho Cha ,  Mun-heui Choi ,  Chang-beom Jeong

发明人： Jong-hwan Kim ,  Gi-ho Cha ,  Mun-heui Choi ,  Chang-beom Jeong

IPC分类号： H01L21/331 ,  H01L21/762

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

摘要翻译： 对半导体装置的SOI衬底的制造方法进行说明。 该方法包括在第一半导体衬底中形成低密度杂质区域和在低密度杂质区域形成高密度杂质区域，形成围绕低密度杂质区域和高密度杂质区域的沟槽，沟槽深度更深 比低密度杂质区域浅，浅于低密度杂质区域，在第一半导体衬底的表面上形成绝缘层，以填充沟槽的内部，在绝缘层的表面上附着第二半导体衬底，并且去除 第一半导体衬底的一部分，使得沟槽的底部露出。

公开(公告)号：US06878605B2

公开(公告)日：2005-04-12

申请号：US10441527

申请日：2003-05-19

申请人： Jong-hwan Kim ,  Gi-ho Cha ,  Mun-heui Choi ,  Chang-beom Jeong

发明人： Jong-hwan Kim ,  Gi-ho Cha ,  Mun-heui Choi ,  Chang-beom Jeong

IPC分类号： H01L29/73 ,  H01L21/84 ,  H01L27/12 ,  H01L21/76

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A method of manufacturing an SOI substrate for semiconductor devices is described. The method includes forming a low density impurity region in a first semiconductor substrate and a high density impurity region in the low density impurity region, forming a trench surrounding the low density impurity region and the high density impurity region, the depth of the trench being deeper than the high density impurity region and shallower than the low density impurity region, forming an insulating layer on the surface of the first semiconductor substrate to fill the inside of the trench, attaching a second semiconductor substrate on the surface of the insulating layer, and removing a part of the first semiconductor substrate so that the bottom of the trench is exposed.

摘要翻译： 对半导体装置的SOI衬底的制造方法进行说明。 该方法包括在第一半导体衬底中形成低密度杂质区域和在低密度杂质区域形成高密度杂质区域，形成围绕低密度杂质区域和高密度杂质区域的沟槽，沟槽深度更深 比低密度杂质区域浅，浅于低密度杂质区域，在第一半导体衬底的表面上形成绝缘层，以填充沟槽的内部，在绝缘层的表面上附着第二半导体衬底，并且去除 第一半导体衬底的一部分，使得沟槽的底部露出。

公开(公告)号：US6045892A

公开(公告)日：2000-04-04

申请号：US16791

申请日：1998-01-30

申请人： Ki-hong Lee ,  Gi-ho Cha

发明人： Ki-hong Lee ,  Gi-ho Cha

IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/485 ,  H01L23/532 ,  B32B3/00

CPC分类号： H01L21/76876 ,  H01L21/76841 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S428/901 ,  Y10T428/12486 ,  Y10T428/12528 ,  Y10T428/12576 ,  Y10T428/12743 ,  Y10T428/24917

摘要： Metal wiring structures for integrated circuits include a seed layer formed on an integrated circuit substrate and a wetting layer formed on the seed layer opposite the integrated circuit substrate. A metal wiring layer is formed on the wetting layer opposite the seed layer. The seed layer and the metal wiring layer have the same crystal orientation. In a preferred embodiment, the seed layer is an aluminum layer having (111) crystal orientation and the metal wiring layer includes aluminum having (111) crystal orientation. The metal wiring layer may be aluminum or an aluminum alloy. The wetting layer preferably includes titanium.

摘要翻译： 用于集成电路的金属布线结构包括形成在集成电路基板上的种子层和形成在与集成电路基板相对的种子层上的润湿层。 在与籽晶层相对的润湿层上形成金属布线层。 籽晶层和金属布线层具有相同的晶体取向。 在优选实施例中，种子层是具有（111）晶体取向的铝层，并且金属布线层包括具有（111）晶体取向的铝。 金属布线层可以是铝或铝合金。 润湿层优选包括钛。

公开(公告)号：US5863375A

公开(公告)日：1999-01-26

申请号：US067821

申请日：1998-04-28

申请人： Gi-ho Cha ,  Byoung-hun Lee

发明人： Gi-ho Cha ,  Byoung-hun Lee

IPC分类号： H01L27/12 ,  B26D3/28 ,  B26F3/00 ,  B32B43/00 ,  H01L21/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/30 ,  H01L21/304 ,  H01L21/58 ,  B32B35/00

CPC分类号： B32B43/006 ,  B26D3/28 ,  B26F3/004 ,  H01L21/67092 ,  H01L24/98 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L24/32 ,  H01L24/83 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S134/902 ,  Y10S156/941 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T156/19 ,  Y10T29/49819 ,  Y10T29/49822 ,  Y10T29/53683

摘要： Wafer debonding of a bonded bulk wafer and a device wafer using a liquid jet to avoid scratching of the wafers is provided. The wafer debonder includes a wafer loader having a first stand with a flat upper surface and a second stand located above the first stand having a lower surface slanted with respect to the upper surface of the first stand at a predetermined angle. A first holder is connected to the first stand and a second holder is located on an imaginary surface extended from the lower surface of the second stand for holding the wafers. A liquid jetting nozzle is positioned adjacent the wafer loader to direct a jet of liquid at the interface between the wafers to separate the wafers.

摘要翻译： 提供了使用液体射流的粘合体晶片和器件晶片的晶片剥离以避免晶片的划伤。 晶片剥离器包括具有平坦的上表面的第一支架和位于第一支架上方的第二支架的晶片装载器，其具有相对于第一支架的上表面以预定角度倾斜的下表面。 第一保持器连接到第一支架，并且第二保持器位于从第二支架的下表面延伸的假想表面上，用于保持晶片。 液体喷射喷嘴位于晶片装载器附近，以在晶片之间的界面处引导液体射流以分离晶片。

公开(公告)号：US5783022A

公开(公告)日：1998-07-21

申请号：US742938

申请日：1996-10-31

申请人： Gi-ho Cha ,  Byoung-hun Lee

发明人： Gi-ho Cha ,  Byoung-hun Lee

IPC分类号： H01L27/12 ,  B26D3/28 ,  B26F3/00 ,  B32B43/00 ,  H01L21/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/30 ,  H01L21/304 ,  H01L21/58 ,  B32B35/00

CPC分类号： B32B43/006 ,  B26D3/28 ,  B26F3/004 ,  H01L21/67092 ,  H01L24/98 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L24/32 ,  H01L24/83 ,  H01L2924/01004 ,  H01L2924/01033 ,  H01L2924/07802 ,  H01L2924/14 ,  Y10S134/902 ,  Y10S156/941 ,  Y10T156/11 ,  Y10T156/1126 ,  Y10T156/19 ,  Y10T29/49819 ,  Y10T29/49822 ,  Y10T29/53683

摘要： Wafer debonding of a bonded bulk wafer and a device wafer using a liquid jet to avoid scratching of the wafers is provided. The wafer debonder includes a wafer loader having a first stand with a flat upper surface and a second stand located above the first stand having a lower surface slanted with respect to the upper surface of the first stand at a predetermined angle. A first holder is connected to the first stand and a second holder is located on an imaginary surface extended from the lower surface of the second stand for holding the wafers. A liquid jetting nozzle is positioned adjacent the wafer loader to direct a jet of liquid at the interface between the wafers to separate the wafers.