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公开(公告)号：US09490429B2
公开(公告)日：2016-11-08
申请号：US14860349
申请日：2015-09-21
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Akio Shima , Kenzo Kurotsuchi , Takashi Kobayashi
IPC: H01L45/00 , H01L27/06 , H01L27/102 , H01L29/792 , H01L27/24 , H01L27/115 , G11C13/00
CPC classification number: H01L45/1608 , G11C13/0004 , G11C2213/75 , H01L27/0688 , H01L27/1021 , H01L27/11578 , H01L27/11582 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L27/249 , H01L29/7926 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/1253 , H01L45/144 , H01L45/16 , H01L45/1675
Abstract: When a thin channel semiconductor layer formed on a side wall of a stacked film in which insulating films and gate electrodes are alternately stacked together is removed on the stacked film, a contact resistance between a vertical transistor including the channel semiconductor layer and the gate electrode, and a bit line formed on the stacked film is prevented from rising. As its means, a conductive layer electrically connected to the channel semiconductor layer is disposed immediately above the stacked film.
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公开(公告)号：US20140103287A1
公开(公告)日：2014-04-17
申请号：US14046984
申请日：2013-10-06
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
IPC: H01L45/00
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
Abstract translation: 公开了一种半导体存储装置及其制造方法。 存储装置具有：基板; 衬底上的第一个字线; 第一层叠体，位于第一字线上方，并且具有N + 1个第一栅极间绝缘层和N个第一半导体层交替层叠; 位于所述层叠体上方并沿与所述第一字线相交的方向延伸的第一位线; 在所述第一栅极绝缘层和所述第一半导体层的侧表面上的第一栅极绝缘层; 在所述第一栅极绝缘层的侧表面上的第一沟道层; 以及在第一沟道层的侧表面上的第一可变电阻材料层。 第一可变电阻材料层在第一字线和第一位线相交的区域中。 多晶硅二极管用作选择元件。
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公开(公告)号：US20140361241A1
公开(公告)日：2014-12-11
申请号：US14468513
申请日：2014-08-26
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
Abstract translation: 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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公开(公告)号：US20160005969A1
公开(公告)日：2016-01-07
申请号：US14857217
申请日：2015-09-17
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
IPC: H01L45/00
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
Abstract translation: 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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5.发明授权公开(公告)号：US09070621B2
公开(公告)日：2015-06-30
申请号：US14076261
申请日：2013-11-10
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Masaharu Kinoshita , Mitsuharu Tai , Takashi Kobayashi
IPC: H01L27/24 , H01L27/102
CPC classification number: H01L27/2481 , H01L27/1021 , H01L27/2409 , H01L27/2436 , H01L27/2472
Abstract: In a nonvolatile semiconductor memory device, there is provided a technique which promotes microfabrication by reducing a thickness of the device as suppressing an OFF current of a polysilicon diode which is a selective element. A polysilicon layer to which an impurity is doped at low concentration and which becomes an electric-field relaxation layer of the polysilicon diode which is a selective element of a resistance variable memory is formed so as to be divided into two or more layers such as polysilicon layers. In this manner, it is suppressed to form the crystal grain boundaries thoroughly penetrating between an n-type polysilicon layer and a p-type polysilicon layer in the electric-field relaxation layer, and therefore, it is prevented to generate a leakage current flowing through the crystal grain boundaries in application of a reverse-bias voltage without increasing a height of the polysilicon diode.
Abstract translation: 在非易失性半导体存储器件中，提供了一种通过减小作为选择元件的多晶硅二极管的截止电流来减小器件厚度来促进微细加工的技术。 形成以低浓度掺杂有杂质并作为电阻可变存储器的选择元件的多晶硅二极管的电场弛豫层的多晶硅层，以被分成两层或多层，例如多晶硅 层。 以这种方式抑制电场弛豫层中的n型多晶硅层和p型多晶硅层之间的晶粒边界完全透过，从而防止产生流过的漏电流 在不增加多晶硅二极管的高度的情况下施加反偏压的晶界。
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Patent Agency Ranking
公开(公告)号：US09873137B2
公开(公告)日：2018-01-23
申请号：US14799632
申请日：2015-07-15
Applicant: HITACHI, LTD.
Inventor： Shuntaro Machida , Takashi Kobayashi
CPC classification number: B06B1/0292 , B81C1/00158 , B81C1/00182 , B81C1/00214 , B81C1/00476 , B81C1/00531 , B81C1/00611 , B81C2201/0104 , B81C2201/0107 , B81C2201/0109 , C09K13/00 , C23F4/00 , H01L21/30604 , H01L29/84 , Y10T29/49156
Abstract: Disclosed is an ultrasonic transducer that is provided with: a bottom electrode; an electric connection part which is connected to the bottom electrode from the bottom of the bottom electrode; a first insulating film which is formed so as to cover the bottom electrode; a cavity which is formed on the first insulating film so as to overlap the bottom electrode when seen from above; a second insulating film which is formed so as to cover the cavity; and a top electrode which is formed on the second insulating film so as to overlap the cavity when seen from above. The electric connection part to the bottom electrode is positioned so as to not overlap the cavity when seen from above.
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公开(公告)号：US09385320B2
公开(公告)日：2016-07-05
申请号：US14857217
申请日：2015-09-17
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
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公开(公告)号：US09153775B2
公开(公告)日：2015-10-06
申请号：US14468513
申请日：2014-08-26
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a method for manufacturing the semiconductor storage device, whereby the bit cost of memory using a variable resistance material is reduced. The semiconductor storage device has: a substrate; a first word line (2) which is provided above the substrate; a first laminated body, which is disposed above the first word line (2), and which has the N+1 (N≧1) number of first inter-gate insulating layers (11-15) and the N number of first semiconductor layers (21p-24p) alternately laminated in the height direction of the substrate; a first bit line (3), which extends in the direction that intersects the first word line (2), and which is disposed above the laminated body; a first gate insulating layer (9) which is provided on the side surface of the N+1 number of the first inter-gate insulating layers (11-15) and those of the N number of the first semiconductor layers (21p-24p); a first channel layer (8p) which is provided on the side surface of the first gate insulating layer (9); and a first variable resistance material layer (7) which is provided on the side surface of the first channel layer. The first variable material layer (7) is in a region where the first word line (2) and the first bit line (3) intersect each other. Furthermore, a polysilicon diode (PD) is used as a selection element.
Abstract translation: 公开了一种半导体存储装置和用于制造半导体存储装置的方法，由此降低了使用可变电阻材料的存储器的位成本。 半导体存储装置具有：基板; 设置在基板上方的第一字线（2） 第一层叠体，其设置在第一字线（2）的上方，并且具有N + 1（N≥1）个第一栅极间绝缘层（11-15）和N个第一半导体层 （21p-24p）在基板的高度方向上交替层叠; 第一位线（3），其在与所述第一字线（2）相交的方向上延伸，并且位于所述层叠体的上方; 设置在N + 1个第一栅极绝缘层（11-15）的侧表面和N个第一半导体层（21p-24p）的侧表面上的第一栅极绝缘层（9） ; 设置在第一栅极绝缘层（9）的侧面上的第一沟道层（8p）; 以及设置在第一沟道层的侧表面上的第一可变电阻材料层（7）。 第一可变材料层（7）在第一字线（2）和第一位线（3）彼此相交的区域中。 此外，使用多晶硅二极管（PD）作为选择元件。
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公开(公告)号：US08841646B2
公开(公告)日：2014-09-23
申请号：US14046984
申请日：2013-10-06
Applicant: Hitachi, Ltd.
Inventor： Yoshitaka Sasago , Akio Shima , Satoru Hanzawa , Takashi Kobayashi , Masaharu Kinoshita , Norikatsu Takaura
CPC classification number: H01L45/1666 , H01L27/224 , H01L27/2409 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/12 , H01L45/1206 , H01L45/1233 , H01L45/144 , H01L45/1608 , H01L45/1641 , H01L45/1675 , H01L45/1683
Abstract: Disclosed are a semiconductor storage device and a manufacturing method. The storage device has: a substrate; a first word line above the substrate; a first laminated body above the first word line and having N+1 first inter-gate insulating layers and N first semiconductor layers alternately laminated; a first bit line above the laminated body and extending in a direction that intersects the first word line; a first gate insulating layer on side surfaces of the first inter-gate insulating layers and the first semiconductor layers; a first channel layer on the side surface of the first gate insulating layer; and a first variable resistance material layer on the side surface of the first channel layer. The first variable resistance material layer is in a region where the first word line and the first bit line intersect. A polysilicon diode is used as a selection element.
Abstract translation: 公开了一种半导体存储装置及其制造方法。 存储装置具有：基板; 衬底上的第一个字线; 第一层叠体，位于第一字线上方，并且具有N + 1个第一栅极间绝缘层和N个第一半导体层交替层叠; 位于所述层叠体上方并沿与所述第一字线相交的方向延伸的第一位线; 在所述第一栅极绝缘层和所述第一半导体层的侧表面上的第一栅极绝缘层; 在所述第一栅极绝缘层的侧表面上的第一沟道层; 以及在第一沟道层的侧表面上的第一可变电阻材料层。 第一可变电阻材料层在第一字线和第一位线相交的区域中。 多晶硅二极管用作选择元件。
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公开(公告)号：US09911916B2
公开(公告)日：2018-03-06
申请号：US15128395
申请日：2014-03-28
Applicant: HITACHI, LTD.
Inventor： Yoshihisa Fujisaki , Yoshitaka Sasago , Takashi Kobayashi
IPC: H01L45/00 , C23C16/22 , C23C16/448 , H01L27/24
CPC classification number: H01L45/1616 , C23C16/22 , C23C16/4482 , C23C16/452 , C23C16/45561 , H01L27/2481 , H01L45/06 , H01L45/1233 , H01L45/144
Abstract: In order to form a phase change thin film being flat in a nanometer level and having a good coverage, which is essential for realizing a three-dimensional ultra-high integrated phase change memory, an equipment for vapor phase growth of a phase change thin film is provided which form a phase change thin film at low temperature while the film is being kept in a completely amorphous state. A structure is provided in which an ammonia cracker is connected to a reactor of the equipment for vapor phase growth for a nitrogen radical obtained by decomposing ammonia gas. Consequently, low temperature decomposition of metal organic precursor and film formation on a substrate surface are realized. With the use of this equipment, it is possible to realize a completely amorphous film which has a flat surface at a low temperature of 135° C. using an amine complex as a Ge precursor.
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