公开(公告)号：US20090236639A1

公开(公告)日：2009-09-24

申请号：US12475839

申请日：2009-06-01

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： H01L29/66

CPC分类号： H01L27/11206 ,  H01L21/76895 ,  H01L23/50 ,  H01L23/5252 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/1052 ,  H01L2924/0002 ,  H01L2924/00

摘要： An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

摘要翻译： 一种非易失性存储器件的布置，其具有至少一个在半导体衬底上层次级别堆叠的存储器件级，每个存储器级包括基本上设置在半导体衬底之上的氧化物层，基本上设置在氧化物层上方的多条字线; 基本上设置在所述氧化物层上方的多个位线; 基本上与字线电接触的多个通孔插塞和基本上设置在位线旁边的侧壁上且与多个位线侧壁反熔丝电介质基本上接触的抗熔丝电介质材料。

公开(公告)号：US20130094273A1

公开(公告)日：2013-04-18

申请号：US13706001

申请日：2012-12-05

申请人： WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

发明人： WEI-CHIH CHIEN ,  MING-HSIU LEE ,  HSIANG-LAN LUNG

IPC分类号： G11C5/06

CPC分类号： G11C5/06 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/2454 ,  H01L27/249 ,  H01L28/24 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/1633

摘要： A 3D memory device is based on an array of conductive pillars and a plurality of patterned conductor planes including left side and right side conductors adjacent the conductive pillars at left side and right side interface regions. Memory elements in the left side and right side interface regions comprise a programmable transition metal oxide which can be characterized by built-in self-switching behavior, or other programmable resistance material. The conductive pillars can be selected using two-dimensional decoding, and the left side and right side conductors in the plurality of planes can be selected using decoding on a third dimension, combined with left and right side selection.

摘要翻译： 3D存储器件基于导电柱阵列和多个图案化的导体平面，其包括在左侧和右侧界面区域处邻近导电柱的左侧和右侧导体。 左侧和右侧界面区域中的存储元件包括可以通过内置自切换行为表征的可编程过渡金属氧化物或其它可编程电阻材料。 可以使用二维解码来选择导电柱，并且可以使用与左侧和右侧选择相结合的第三维度上的解码来选择多个平面中的左侧和右侧导体。

公开(公告)号：US20120231613A1

公开(公告)日：2012-09-13

申请号：US13476964

申请日：2012-05-21

申请人： HSIANG-LAN LUNG ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING HSIU LEE ,  HANG-TING LUE

发明人： HSIANG-LAN LUNG ,  YEN-HAO SHIH ,  ERH-KUN LAI ,  MING HSIU LEE ,  HANG-TING LUE

IPC分类号： H01L21/20

CPC分类号： G11C16/0458 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/11578 ,  H01L27/11582

摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.

摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。 半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。 半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。 电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。 该设备可以作为3D和解码的闪存操作。

公开(公告)号：US20120181599A1

公开(公告)日：2012-07-19

申请号：US13070323

申请日：2011-03-23

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/792

摘要： An integrated circuit device is described that includes a 3D memory comprising a plurality of self-aligned stacks of word lines orthogonal to and interleaved with a plurality of self-aligned stacks of bit lines. Data storage structures such as dielectric charge storage structures, are provided at cross points between word lines and bit lines in the plurality of self-aligned stacks of word lines interleaved with the plurality of self-aligned stacks of bit lines.

摘要翻译： 描述了一种集成电路装置，其包括3D存储器，该3D存储器包括多个自对准堆叠的字线，其与多个自对准堆叠的位线正交并交错。 诸如介电电荷存储结构之类的数据存储结构被提供在与多条自对准堆叠的位线交错的字线的多个自对齐堆叠中的字线和位线之间的交叉点处。

公开(公告)号：US20110084397A1

公开(公告)日：2011-04-14

申请号：US12579192

申请日：2009-10-14

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/522 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11206 ,  H01L27/11286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional 3D interconnect structure with a small footprint is described, useful for connection from above to levels of circuit structures in a multi-level device. Also, an efficient and low cost method for manufacturing the 3D interconnect structure is provided.

摘要翻译： 描述了具有小占地面积的三维3D互连结构，其用于从多层设备中的上述电路结构层次的连接。 另外，提供了用于制造3D互连结构的有效且低成本的方法。

公开(公告)号：US20110013446A1

公开(公告)日：2011-01-20

申请号：US12503566

申请日：2009-07-15

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C11/5678 ,  G11C13/0033 ,  G11C13/004 ,  G11C16/3431

摘要： A memory device as described herein includes a reference array of phase change memory cells and a memory array of phase change memory cells, where a difference between a current data set stored in the reference array and an expected data set is used to determine when to refresh the memory array. The high resistance state for the reference array is a “partial reset” state having a minimum resistance less than that of the high resistance state for the memory array. Sense circuitry is adapted to read the memory cells of the reference array and to generate a refresh command signal if there is a difference between a current data set stored in the reference array and an expected data set, and control circuitry responsive to the refresh command signal to perform a refresh operation on the memory cells of the memory array.

摘要翻译： 如本文所述的存储器件包括相变存储器单元的参考阵列和相变存储器单元的存储器阵列，其中存储在参考阵列中的当前数据集与预期数据集之间的差用于确定何时刷新 内存阵列。 用于参考阵列的高电阻状态是具有比用于存储器阵列的高电阻状态的最小电阻的最小电阻的“部分复位”状态。 感测电路适于读取参考阵列的存储器单元，并且如果存储在参考阵列中的当前数据集与预期数据组之间存在差异，则产生刷新命令信号，以及响应于刷新命令信号的控制电路 对存储器阵列的存储单元执行刷新操作。

公开(公告)号：US20100296328A1

公开(公告)日：2010-11-25

申请号：US12841969

申请日：2010-07-22

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： G11C17/16

CPC分类号： G11C17/00 ,  H01L23/5252 ,  H01L27/1021 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An anti-fuse one-time-programmable (OTP) nonvolatile memory cell has a P well substrate with two P.sup.-doped regions. Another N.sup.+doped region, functioning as a bit line, is positioned adjacent and between the two P.sup.-doped regions on the substrate. An anti-fuse is defined over the N.sup.+doped region. Two insulator regions are deposited over the two P.sup.-doped regions. An impurity doped polysilicon layer is defined over the two insulator regions and the anti-fuse. A polycide layer is defined over the impurity doped polysilicon layer. The polycide layer and the polysilicon layer function as a word line. A programmed region, i.e., a link, functioning as a diode, is formed on the anti-fuse after the anti-fuse OTP nonvolatile memory cell is programmed. The array structure of anti-fuse OTP nonvolatile memory cells and methods for programming, reading, and fabricating such a cell are also disclosed.

摘要翻译： 反熔丝一次可编程（OTP）非易失性存储单元具有具有两个掺杂Ps的掺杂区的P阱衬底。 用作位线的另一个N.sup +掺杂区位于衬底上的两个掺杂Ps的掺杂区之间。 在N.sup +掺杂区域上定义了反熔丝。 两个绝缘体区域沉积在两个掺杂Ps的掺杂区域上。 在两个绝缘体区域和反熔丝上限定杂质掺杂多晶硅层。 在杂质掺杂多晶硅层上限定多晶硅化物层。 多晶硅层和多晶硅层用作字线。 在反熔丝OTP非易失性存储单元被编程之后，在反熔丝上形成用作二极管的编程区域，即链路。 还公开了反熔丝OTP非易失性存储单元的阵列结构以及用于编程，读取和制造这种单元的方法。

公开(公告)号：US20090184310A1

公开(公告)日：2009-07-23

申请号：US12016840

申请日：2008-01-18

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： H01L47/00 ,  H01L21/311

CPC分类号： H01L45/1625 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/144 ,  H01L45/16

摘要： Memory cells are described along with methods for manufacturing. A memory cell described herein includes a bottom electrode comprising a base portion and a pillar portion on the base portion, the pillar portion having a top surface and a width less than that of the base portion. A memory element is on the top surface of the pillar portion and comprises memory material having at least two solid phases. A top electrode is on the memory element.

摘要翻译： 描述存储单元以及制造方法。 本文所述的存储单元包括底部电极，其包括基部和基部上的柱部，所述柱部具有顶表面和宽度小于基部的宽度。 存储元件位于柱部分的顶表面上并且包括具有至少两个固相的记忆材料。 顶部电极位于存储元件上。

公开(公告)号：US20140042382A1

公开(公告)日：2014-02-13

申请号：US13570660

申请日：2012-08-09

申请人： HSIANG-LAN LUNG

发明人： HSIANG-LAN LUNG

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/2463 ,  G11C13/0004 ,  G11C2213/72 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/16

摘要： A memory device includes a first conductor, a diode, a memory element, and a second conductor arranged in series. The diode includes a first semiconductor layer over and in electrical communication with the first conductor. A patterned insulating layer has a sidewall over the first semiconductor layer. The diode includes an intermediate semiconductor layer on a first portion of the sidewall, and in contact with the first semiconductor layer. The intermediate semiconductor layer has a lower carrier concentration than the first semiconductor layer, and can include an intrinsic semiconductor. A second semiconductor layer on a second portion of the sidewall, and in contact with the intermediate semiconductor layer, has a higher carrier concentration than the intermediate semiconductor layer. A memory element is electrically coupled to the second semiconductor layer. The second conductor is electrically coupled to the memory element.

摘要翻译： 存储器件包括串联布置的第一导体，二极管，存储元件和第二导体。 二极管包括在第一导体上并与之电气连通的第一半导体层。 图案化绝缘层在第一半导体层上具有侧壁。 二极管包括在侧壁的第一部分上并与第一半导体层接触的中间半导体层。 中间半导体层具有比第一半导体层低的载流子浓度，并且可以包括本征半导体。 在侧壁的第二部分上并与中间半导体层接触的第二半导体层具有比中间半导体层更高的载流子浓度。 存储元件电耦合到第二半导体层。 第二导体电耦合到存储元件。

公开(公告)号：US20130056699A1

公开(公告)日：2013-03-07

申请号：US13670337

申请日：2012-11-06

申请人： HSIANG-LAN LUNG ,  CHUNG HON LAM

发明人： HSIANG-LAN LUNG ,  CHUNG HON LAM

IPC分类号： H01L45/00

CPC分类号： H01L27/101 ,  G11C13/0004 ,  H01L27/2454 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/142 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1625 ,  H01L45/1641 ,  H01L45/1675 ,  H01L45/1683

摘要： A device includes a substrate having a first region and a second region. The first region comprises a first field effect transistor having a horizontal channel region within the substrate, a gate overlying the horizontal channel region, and a first dielectric covering the gate of the first field effect transistor. The second region of the substrate includes a second field effect transistor comprising a first terminal extending through the first dielectric to contact the substrate, a second terminal overlying the first terminal and having a top surface, and a vertical channel region separating the first and second terminals. The second field effect transistor also includes a gate on the first dielectric and adjacent the vertical channel region, the gate having a top surface that is co-planar with the top surface of the second terminal.

摘要翻译： 一种器件包括具有第一区域和第二区域的衬底。 第一区域包括在衬底内具有水平沟道区的第一场效应晶体管，覆盖在水平沟道区上的栅极和覆盖第一场效应晶体管的栅极的第一电介质。 衬底的第二区域包括第二场效应晶体管，其包括延伸穿过第一电介质以接触衬底的第一端子，覆盖第一端子并具有顶表面的第二端子和分离第一和第二端子的垂直沟道区域 。 第二场效应晶体管还包括在第一电介质上并且与垂直沟道区相邻的栅极，栅极具有与第二端子的顶表面共面的顶表面。