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    Method for forming ferrocapacitors and FeRAM devices
    1.
    发明申请
    Method for forming ferrocapacitors and FeRAM devices 审中-公开
    形成铁电体和FeRAM器件的方法

    公开(公告)号：US20050084984A1

    公开(公告)日：2005-04-21

    申请号：US10678952

    申请日：2003-10-02

    申请人： Haoren Zhuang ,  Rainer Bruchhaus ,  Ulrich Egger ,  Jenny Lian ,  Nicolas Nagel

    发明人： Haoren Zhuang ,  Rainer Bruchhaus ,  Ulrich Egger ,  Jenny Lian ,  Nicolas Nagel

    IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L31/119

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55

    摘要： A vertical capacitor of an FeRAM device is formed by depositing conductive material and etching it to form electrodes, which are located over openings in an insulating layer so that they are electrically connected to lower levels of the structure. A layer of ferroelectric material is formed on the sides of the electrodes, and etched to a desired, uniform thickness. Conductive material is deposited over the ferroelectric material to form a uniform surface onto which another insulating layer can be deposited. Since this process does not include etching of an insulating layer at a time between the formation of the electrodes and the deposition of the ferroelectric material, no fences of insulating material are formed between them. The geometry can be accurately controlled, to give uniform electric fields and reliable operating parameters.

    摘要翻译： FeRAM器件的垂直电容器通过沉积导电材料并进行蚀刻而形成，以形成位于绝缘层中的开口上方的电极，使得它们电连接到结构的较低层。 在电极的侧面形成铁电材料层，并且蚀刻到期望的均匀厚度。 导电材料沉积在铁电材料上以形成可沉积另一绝缘层的均匀表面。 由于该方法不包括在形成电极之间的时间刻蚀绝缘层和铁电体的沉积，所以在它们之间不形成绝缘材料栅栏。 几何形状可以精确控制，给出均匀的电场和可靠的工作参数。

    Device and a method for forming a capacitor device
    2.
    发明授权
    Device and a method for forming a capacitor device 失效
    装置及形成电容器装置的方法

    公开(公告)号：US07041551B2

    公开(公告)日：2006-05-09

    申请号：US10677099

    申请日：2003-09-30

    申请人： Haoren Zhuang ,  Nicolas Nagel ,  Jenny Lian ,  Rainer Bruchhaus

    发明人： Haoren Zhuang ,  Nicolas Nagel ,  Jenny Lian ,  Rainer Bruchhaus

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/92

    摘要： A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.

    摘要翻译： 用于形成电容器器件的器件和方法包括形成衬底，在衬底上形成第一层间电介质层，并通过衬底形成两个或更多个接触插塞。 在第一层间电介质层上形成导电层，通过蚀刻导电层，在交替的接触插塞上形成电极。 然后用铁电层涂覆蚀刻的电极。 从分离接触塞的表面蚀刻铁电层，并且通过用导电材料填充交替的接触插塞上的电极之间的空间来产生附加电极，以建立插塞和电极之间的电接触。

    Device and a method for forming a capacitor device
    3.
    发明申请
    Device and a method for forming a capacitor device 失效
    装置及形成电容器装置的方法

    公开(公告)号：US20050067644A1

    公开(公告)日：2005-03-31

    申请号：US10677099

    申请日：2003-09-30

    申请人： Haoren Zhuang ,  Nicolas Nagel ,  Jenny Lian ,  Rainer Bruchhaus

    发明人： Haoren Zhuang ,  Nicolas Nagel ,  Jenny Lian ,  Rainer Bruchhaus

    IPC分类号： H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

    CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/92

    摘要： A device and method for forming a capacitor device comprises forming a substrate, forming a first interlayer dielectric layer on the substrate and forming two or more contact plugs through the substrate. A conducting layer is formed on the first interlayer dielectric layer and an electrode is formed on alternate ones of the contact plugs by etching the conducting layer. The etched electrodes are then coated with a ferroelectric layer. The ferroelectric layer is etched from the surfaces separating the contact plugs and additional electrodes are created by filling the spaces between the electrodes on alternate ones of the contact plugs with a conductive material to establish electrical contact between the plugs and the electrodes.

    摘要翻译： 用于形成电容器器件的器件和方法包括形成衬底，在衬底上形成第一层间电介质层，并通过衬底形成两个或更多个接触插塞。 在第一层间电介质层上形成导电层，通过蚀刻导电层，在交替的接触插塞上形成电极。 然后用铁电层涂覆蚀刻的电极。 从分离接触塞的表面蚀刻铁电层，并且通过用导电材料填充交替的接触插塞上的电极之间的空间来产生附加电极，以建立插塞和电极之间的电接触。

    Side-wall barrier structure and method of fabrication
    5.
    发明授权
    Side-wall barrier structure and method of fabrication 有权
    侧壁屏障结构及其制造方法

    公开(公告)号：US06946735B2

    公开(公告)日：2005-09-20

    申请号：US10307257

    申请日：2002-11-29

    申请人： Stefan Gernhardt ,  Jenny Lian ,  Andreas Hilliger ,  Rainer Bruchhaus ,  Uwe Wellhausen ,  Nicolas Nagel

    发明人： Stefan Gernhardt ,  Jenny Lian ,  Andreas Hilliger ,  Rainer Bruchhaus ,  Uwe Wellhausen ,  Nicolas Nagel

    IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L23/48

    CPC分类号： H01L21/7687 ,  H01L21/76877 ,  H01L28/60

    摘要： The invention includes a wafer having a poly silicon plug passing through a CP-contact. The poly silicon plug is formed from a relatively heavily doped poly silicon layer and a relatively lightly doped poly silicon layer. The relatively lightly doped poly silicon layer passes through the relatively heavily doped poly silicon layer to extend beyond the relatively heavily doped poly silicon layer towards the surface of the wafer. A barrier layer covers top and side walls of the relatively lightly doped poly silicon layer for reducing oxidation at the surface of the poly silicon plug. The wafer is fabricated by depositing a relatively heavily doped poly silicon layer in a CP-contact, depositing a relatively lightly doped poly silicon layer to pass through the relatively heavily doped poly silicon layer, and depositing a barrier layer to cover top and side walls of the relatively lightly doped poly silicon layer to reduce oxidation at the surface of the poly silicon plug.

    摘要翻译： 本发明包括具有通过CP接触的多硅插头的晶片。 多晶硅插头由相对高掺杂的多晶硅层和相对轻掺杂的多晶硅层形成。 相对轻掺杂的多晶硅层通过相对重掺杂的多晶硅层延伸超过相对重掺杂的多晶硅层朝向晶片的表面。 阻挡层覆盖相对较轻掺杂的多晶硅层的顶壁和侧壁，用于减少多晶硅插头表面的氧化。 通过在CP接触中沉积相对重掺杂的多晶硅层来制造晶片，沉积相对轻掺杂的多晶硅层以通过相对重掺杂的多晶硅层，以及沉积阻挡层以覆盖顶部和侧壁 相对轻掺杂的多晶硅层，以减少在多晶硅塞的表面处的氧化。

    Process for fabrication of a ferroelectric capacitor
    6.
    发明授权
    Process for fabrication of a ferroelectric capacitor 失效
    铁电电容器制造工艺

    公开(公告)号：US07199002B2

    公开(公告)日：2007-04-03

    申请号：US10651614

    申请日：2003-08-29

    申请人： Karl Hornik ,  Rainer Bruchhaus ,  Nicolas Nagel

    发明人： Karl Hornik ,  Rainer Bruchhaus ,  Nicolas Nagel

    IPC分类号： H01L27/108

    CPC分类号： H01L28/56 ,  H01L21/31616 ,  H01L21/31683

    摘要： A process for the fabrication of a ferroelectric capacitor comprising depositing a layer of Ti 5 over an insulating layer 3 of Al2O3, and oxidising the Ti layer to form a TiO2 layer 7. Subsequently, a layer of PZT 9 is formed over the TiO2 layer 7. The PZT layer 9 is subjected to an annealing step in which, due to the presence of the TiO2 layer 7 it crystallises to form a layer 11 with a high degree of (111)-texture.

    摘要翻译： 一种用于制造铁电电容器的方法，包括在Al 2 O 3 3的绝缘层3上沉积Ti 5层，并氧化Ti层以形成TiO 然后，在TiO 2层7上形成PZT 9层.PZT层9经历退火步骤，其中由于 TiO 2层7的存在使其结晶形成具有高度（111） - 纹理的层11。

    Self-aligned V0-contact for cell size reduction
    10.
    发明申请
    Self-aligned V0-contact for cell size reduction 失效
    自对准V0接触用于电池尺寸减小

    公开(公告)号：US20060151819A1

    公开(公告)日：2006-07-13

    申请号：US11373080

    申请日：2006-03-09

    申请人： Jingyu Lian ,  Nicolas Nagel ,  Stefan Gernhardt ,  Rainer Bruchhaus ,  Andreas Hilliger ,  Uwe Wellhausen

    发明人： Jingyu Lian ,  Nicolas Nagel ,  Stefan Gernhardt ,  Rainer Bruchhaus ,  Andreas Hilliger ,  Uwe Wellhausen

    IPC分类号： H01L29/94

    CPC分类号： H01L21/76897 ,  H01L28/55

    摘要： An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.

    摘要翻译： FeRAM包括夹在顶电极和底电极之间的铁电材料。 V0触点提供与底层CS触点的电气连接。 使用底部电极对齐V0触点。 衬里层覆盖底部电极的侧壁，并为蚀刻形成V0接触的孔提供停止。 在FeRAM中使用一种形成V0接触的方法，包括。 FeRAM的Fe电容器被封装，蚀刻底部电极，沉积覆盖底部电极的侧壁的衬层，并且蚀刻用于V0接触的孔，直到蚀刻被衬垫层停止。