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    FENCE-FREE ETCHING OF IRIDIUM BARRIER HAVING A STEEP TAPER ANGLE
    3.
    发明申请
    FENCE-FREE ETCHING OF IRIDIUM BARRIER HAVING A STEEP TAPER ANGLE 失效
    具有椎弓根角度的UM。。。。。。。。。。。。。。。。

    公开(公告)号：US20050045937A1

    公开(公告)日：2005-03-03

    申请号：US10654376

    申请日：2003-09-03

    申请人： Ulrich Egger ,  Haoren Zhuang ,  George Stojakovic ,  Kazuhiro Tomioka

    发明人： Ulrich Egger ,  Haoren Zhuang ,  George Stojakovic ,  Kazuhiro Tomioka

    IPC分类号： H01L21/02 ,  H01L21/3213 ,  H01L21/8246 ,  H01L21/00 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L28/60 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    摘要： An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

    摘要翻译： 铱屏障层位于电容器的接触插塞和底部电极之间。 进行蚀刻以使用氟基配方对底部电极和阻挡层进行图案化，从而形成紧贴在侧壁上的第一栅栏。 接下来，使用基于CO的配方蚀刻剩余的阻挡层。 第二个围栏是由第一个围栏固定在结构上。 同时，基于CO的配方消除了第一篱笆的大部分，以移除提供给第二篱笆的结构支撑。 因此，第二围栏从侧壁脱离，留下侧壁基本上没有附着的栅栏。 蚀刻的阻挡层具有侧壁过渡。 侧壁在侧壁过渡之上具有相对较低的锥角，并且在侧壁过渡之下具有相对较陡的锥角。

    Fence-free etching of iridium barrier having a steep taper angle
    4.
    发明授权
    Fence-free etching of iridium barrier having a steep taper angle 失效
    无ence蚀刻具有陡峭锥角的铱屏障

    公开(公告)号：US07015049B2

    公开(公告)日：2006-03-21

    申请号：US10654376

    申请日：2003-09-03

    申请人： Ulrich Egger ,  Haoren Zhuang ,  George Stojakovic ,  Kazuhiro Tomioka

    发明人： Ulrich Egger ,  Haoren Zhuang ,  George Stojakovic ,  Kazuhiro Tomioka

    IPC分类号： H01L21/00

    CPC分类号： H01L28/60 ,  H01L21/32136 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

    摘要： An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

    摘要翻译： 铱屏障层位于电容器的接触插塞和底部电极之间。 进行蚀刻以使用氟基配方对底部电极和阻挡层进行图案化，从而形成紧贴在侧壁上的第一栅栏。 接下来，使用基于CO的配方蚀刻剩余的阻挡层。 第二个围栏是由第一个围栏固定在结构上。 同时，基于CO的配方消除了第一篱笆的大部分，以移除提供给第二篱笆的结构支撑。 因此，第二围栏从侧壁脱离，留下侧壁基本上没有附着的栅栏。 蚀刻的阻挡层具有侧壁过渡。 侧壁在侧壁过渡之上具有相对较低的锥角，并且在侧壁过渡之下具有相对较陡的锥角。

    Process for fabrication of a ferrocapacitor
    5.
    发明授权
    Process for fabrication of a ferrocapacitor 失效
    制造铁电体的方法

    公开(公告)号：US06762064B1

    公开(公告)日：2004-07-13

    申请号：US10417526

    申请日：2003-04-17

    申请人： Haoren Zhuang ,  Ulrich Egger ,  Kazuhiro Tomioka

    发明人： Haoren Zhuang ,  Ulrich Egger ,  Kazuhiro Tomioka

    IPC分类号： H01L2100

    CPC分类号： H01L28/55 ,  H01L21/32139 ,  H01L27/11507 ,  H01L28/60

    摘要： A process for the fabrication of a ferrocapacitor comprising depositing a first mask element 7 over a structure having a bottom electrode 1, a ferroelectric layer 3 and a top electrode 5. RIE etching is performed to remove portions of the top electrode 5 and the ferroelectric layer 3. Then a second hard mask element 9 is deposited over the first hardmask element. The second hard mask element is rounded by an etch back process, and its taper angle is controlled to be in the range 75-87°. A second RIE etching process is performed to remove portions of the bottom electrode 1. Due to the rounding of the second hard mask elements 9 low residues are formed on the sides of the etched bottom electrode 1.

    摘要翻译： 一种用于制造铁电体的方法，包括在具有底部电极1，铁电体层3和顶部电极5的结构上沉积第一掩模元件7.进行RIE蚀刻以去除顶部电极5和铁电层的部分 然后，第二硬掩模元件9沉积在第一硬掩模元件上。 第二个硬掩模元件通过回蚀工艺圆化，其锥角控制在75-87°的范围内。 执行第二RIE蚀刻工艺以去除底部电极1的部分。由于第二硬掩模元件9的四舍五入，在蚀刻的底部电极1的侧面上形成低残留物。

    Method for manufacturing semiconductor device
    6.
    发明授权
    Method for manufacturing semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US07115522B2

    公开(公告)日：2006-10-03

    申请号：US10886668

    申请日：2004-07-09

    申请人： Kazuhiro Tomioka ,  Haoren Zhuang

    发明人： Kazuhiro Tomioka ,  Haoren Zhuang

    IPC分类号： H01I21/302

    CPC分类号： H01L21/02071 ,  H01L21/67069 ,  H01L27/10852 ,  H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/65 ,  H01L28/75

    摘要： A method for manufacturing a semiconductor device including a substrate to be processed having a conductive layer essentially consisting of platinum includes etching the conductive layer, and generating plasma and cleaning the substrate, to which an etching product adhere, by means of ions in the plasma. The cleaning includes heating the substrate to a first temperature, introducing gas, which contains chlorine and nitrogen and in which a ratio of chlorine atoms to nitrogen atoms is 9:1 to 5:5, and applying high-frequency power to an electrode, on which the substrate is placed.

    摘要翻译： 一种用于制造半导体器件的方法，该半导体器件包括具有基本上由铂组成的导电层的待加工衬底，包括蚀刻导电层，并且通过等离子体中的离子产生等离子体并清洁蚀刻产物所附着的衬底。 清洁包括将基板加热到第一温度，引入含有氯和氮的气体，其中氯原子与氮原子的比例为9:1至5:5，并将高频电力施加到电极上 放置基板。

    Semiconductor device and mask pattern
    9.
    发明申请
    Semiconductor device and mask pattern 失效
    半导体器件和掩模图案

    公开(公告)号：US20060231876A1

    公开(公告)日：2006-10-19

    申请号：US11107750

    申请日：2005-04-18

    申请人： Osamu Arisumi ,  Yoshinori Kumura ,  Kazuhiro Tomioka ,  Ulrich Egger ,  Haoran Zhuang ,  Bum-ki Moon

    发明人： Osamu Arisumi ,  Yoshinori Kumura ,  Kazuhiro Tomioka ,  Ulrich Egger ,  Haoran Zhuang ,  Bum-ki Moon

    IPC分类号： H01L29/00

    CPC分类号： H01L28/55 ,  H01L28/65

    摘要： A semiconductor device according to an aspect of the invention comprises a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a side wall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×π/6 [rad]} or more.

    摘要翻译： 根据本发明的一个方面的半导体器件包括半导体衬底和电容器，其设置在半导体衬底之上并且被构造为使得电介质膜夹在下电极和上电极之间，电介质膜由 包含作为A位元素的Pb，Ba和Sr中的至少一种和Zr，Ti，Ta，Nb，Mg，W，Fe中的至少一种的ABO 3钙钛矿型氧化物，和 Co作为B位元素，其中当从上方或膜厚方向观察时，电容器的侧壁的曲率半径为250 [nm]以下，并且具有半径为 曲率为{250 [nm] xpi / 6 [rad]}以上。

    Semiconductor device and mask pattern
    10.
    发明授权
    Semiconductor device and mask pattern 失效
    半导体器件和掩模图案

    公开(公告)号：US07504680B2

    公开(公告)日：2009-03-17

    申请号：US11107750

    申请日：2005-04-18

    申请人： Osamu Arisumi ,  Yoshinori Kumura ,  Kazuhiro Tomioka ,  Ulrich Egger ,  Haoran Zhuang ,  Bum-ki Moon

    发明人： Osamu Arisumi ,  Yoshinori Kumura ,  Kazuhiro Tomioka ,  Ulrich Egger ,  Haoran Zhuang ,  Bum-ki Moon

    IPC分类号： H01L31/062 ,  H01L31/113

    CPC分类号： H01L28/55 ,  H01L28/65

    摘要： A semiconductor device according to an aspect of the invention includes a semiconductor substrate, and a capacitor that is provided above the semiconductor substrate and is configured such that a dielectric film is sandwiched between a lower electrode and an upper electrode, the dielectric film being formed of an ABO3 perovskite-type oxide that includes at least one of Pb, Ba and Sr as an A-site element and at least one of Zr, Ti, Ta, Nb, Mg, W, Fe and Co as a B-site element, wherein a radius of curvature of a sidewall of the capacitor, when viewed from above or in a film thickness direction, is 250 [nm] or less, and a length of an arc with the radius of curvature is {250 [nm]×π/6 [rad]} or less.

    摘要翻译： 根据本发明的一个方面的半导体器件包括半导体衬底和电容器，其设置在半导体衬底之上并且被构造为使得电介质膜夹在下电极和上电极之间，电介质膜由 包含作为A位元素的Pb，Ba和Sr中的至少一种和作为B位元素的Zr，Ti，Ta，Nb，Mg，W，Fe和Co中的至少一种的ABO 3钙钛矿型氧化物， 其中，当从上方或者膜厚方向观察时，电容器的侧壁的曲率半径为250 [nm]以下，曲率半径的弧长为{250 [nm]×ppi / 6 [rad]}以下。