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    CMOS device structures and method of making same
    3.
    发明授权
    CMOS device structures and method of making same 有权
    CMOS器件结构及其制作方法

    公开(公告)号：US06303450B1

    公开(公告)日：2001-10-16

    申请号：US09717971

    申请日：2000-11-21

    申请人： Heemyong Park ,  Anda C. Mocuta ,  Werner Rausch

    发明人： Heemyong Park ,  Anda C. Mocuta ,  Werner Rausch

    IPC分类号： H01L21336

    CPC分类号： H01L29/66772 ,  H01L29/41733 ,  H01L29/78618 ,  H01L29/78684

    摘要： Disclosed is a method comprising providing a silicon surface with an underlying insulator layer, providing a plurality of gates adjacent to source/drain regions, growing source/drains between the said gates such that the source/drains are thicker in regions of larger gate-to-gate pitch, and doping the source/drains with one or more dopants such that the dopants abut the underlying insulator layer.

    摘要翻译： 公开了一种方法，包括向硅表面提供下面的绝缘体层，提供与源极/漏极区域相邻的多个栅极，在所述栅极之间生长源极/漏极，使得源极/漏极在较大的栅极 - - 门间距，并用一种​​或多种掺杂剂掺杂源极/漏极，使得掺杂剂邻接下面的绝缘体层。

    Protection against charging damage in hybrid orientation transistors
    5.
    发明授权
    Protection against charging damage in hybrid orientation transistors 有权
    在混合取向晶体管中防止充电损坏

    公开(公告)号：US07928513B2

    公开(公告)日：2011-04-19

    申请号：US12317310

    申请日：2008-12-22

    申请人： Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

    发明人： Terence B. Hook ,  Anda C. Mocuta ,  Jeffrey W. Sleight ,  Anthony K. Stamper

    IPC分类号： H01L27/12

    CPC分类号： H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

    摘要： A chip can include a CMOS structure having a bulk device disposed in a first region of a semiconductor substrate in conductive communication with an underlying bulk region of the substrate, the first region and the bulk region having a first crystal orientation. An SOI device is disposed in a semiconductor-on-insulator (“SOI”) layer separated from the bulk region of the substrate by a buried dielectric layer, the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor (“PFET”) and the SOI device includes an n-type field effect transistor (“NFET”) device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor in conductive communication with a gate conductor of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

    摘要翻译： 芯片可以包括CMOS结构，其具有设置在半导体衬底的第一区域中的体器件，其与衬底的下面的体区域导电连通，第一区域和体区具有第一晶体取向。 SOI器件设置在绝缘体上半导体（“SOI”）层中，其通过掩埋电介质层与衬底的本体区域分离，SOI层具有与第一晶体取向不同的晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体导通的栅极导体时，除了存在与体区域反向偏置导电连通的二极管之外，SOI器件可能发生充电损坏。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。

    High performance CMOS device structure with mid-gap metal gate
    6.
    发明授权
    High performance CMOS device structure with mid-gap metal gate 失效
    高性能CMOS器件结构，具有中间间隙金属栅极

    公开(公告)号：US06916698B2

    公开(公告)日：2005-07-12

    申请号：US10795672

    申请日：2004-03-08

    申请人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    发明人： Anda C. Mocuta ,  Meikei Ieong ,  Ricky S. Amos ,  Diane C. Boyd ,  Dan M. Mocuta ,  Huajie Chen

    IPC分类号： H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49

    CPC分类号： H01L21/823807 ,  H01L21/823828

    摘要： High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

    摘要翻译： 公开了具有中间间隙功函数金属栅极的高性能（表面沟道）CMOS器件，其中外延层用于PFET区域的阈值电压Vt调整/减小，用于大的Vt降低（〜500mV），如 需要具有中间间隙金属栅极的CMOS器件。 本发明提供了使用原位B掺杂外延层或B和C共掺杂外延层的反掺杂，其中C共掺杂提供了额外的自由度以减少B的扩散（也在随后的激活热循环期间） ）以保持浅的B剖面，这对于提供具有中间间隙金属栅极的表面沟道CMOS器件而言是至关重要的，同时保持良好的短沟道效应。 对于具有中间间隙金属栅极的器件，B扩散曲线令人满意地浅，尖锐且具有高B浓度，以在栅极氧化物下提供并保持薄的高掺杂B层。

    Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors
    7.
    发明授权
    Compact model for device/circuit/chip leakage current (IDDQ) calculation including process induced uplift factors 失效
    紧凑型器件/电路/芯片泄漏电流（IDDQ）计算，包括工艺引起的隆起因素

    公开(公告)号：US08626480B2

    公开(公告)日：2014-01-07

    申请号：US12574440

    申请日：2009-10-06

    申请人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

    发明人： Paul Chang ,  Jie Deng ,  Terrence B. Hook ,  Sim Y. Loo ,  Anda C. Mocuta ,  Jae-Eun Park ,  Kern Rim ,  Xiaojun Yu

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G01R31/2848 ,  G01R31/3008 ,  G06F17/5009 ,  G06F17/5022 ,  G06F17/5036

    摘要： A system, method and computer program product for implementing a quiescent current leakage specific model into semiconductor device design and circuit design flows. The leakage model covers all device geometries with wide temperature and voltage ranges and, without the need for stacking factor calculations nor spread sheet based IDDQ calculations. The leakage model for IDDQ calculation incorporates further parasitic and proximity effects. The leakage model implements leakage calculations at different levels of testing, e.g., from a single device to a full chip design, and are integrated within one single model. The leakage model implements leakage calculations at different levels of testing with the leverage of a single switch setting. The implementation is via a hardware definition language code or object oriented code that can be compiled and operated using a netlist of interest, e.g., for conducting a performance analysis.

    摘要翻译： 一种用于将静态电流泄漏特定模型实现为半导体器件设计和电路设计流程的系统，方法和计算机程序产品。 泄漏模型涵盖宽温度和电压范围的所有器件几何，并且不需要堆叠因子计算，也不需要基于平板的IDDQ计算。 IDDQ计算的泄漏模型包含进一步的寄生和邻近效应。 泄漏模型在不同的测试水平下实施泄漏计算，例如从单个设备到全芯片设计，并且集成在一个单一的模型中。 泄漏模型通过单个开关设置的杠杆来实现不同测试级别的泄漏计算。 该实现是通过硬件定义语言代码或面向对象的代码，其可以使用感兴趣的网表来编译和操作，例如用于进行性能分析。

    Methods and system for analysis and management of parametric yield
    8.
    发明授权
    Methods and system for analysis and management of parametric yield 有权
    参数收益分析与管理方法与系统

    公开(公告)号：US08239790B2

    公开(公告)日：2012-08-07

    申请号：US13216362

    申请日：2011-08-24

    申请人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    发明人： James A. Culp ,  Paul Chang ,  Dureseti Chidambarrao ,  Praveen Elakkumanan ,  Jason Hibbeler ,  Anda C. Mocuta

    IPC分类号： G06F17/50

    CPC分类号： G01R31/26 ,  G06F17/5045

    摘要： Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

    摘要翻译： 对晶体管的导通电流和截止电流对晶体管的物理设计选择的参数性能的影响。 设计参数的影响被纳入测量平均电流和平均截止电流的预测偏差的参数以及测量导通电流和截止电流分布的偏差预测增加的参数。 可以在单元级别，块级或芯片级别进行统计，以在设计阶段优化芯片设计，或者在制造期间或在观察到抑制参数产量之后预测参数产量的变化。 此外，可以逐区域地预测参数产量和电流水平，并与观察到的热发射进行比较，以确定芯片中的任何异常区域，以便在芯片设计中的任何错误中进行检测和校正。

    MOSFET with super-steep retrograded island
    9.
    发明授权
    MOSFET with super-steep retrograded island 失效
    具超级陡峭退火岛的MOSFET

    公开(公告)号：US07723750B2

    公开(公告)日：2010-05-25

    申请号：US11774221

    申请日：2007-07-06

    申请人： Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

    发明人： Huilong Zhu ,  Effendi Leobandung ,  Anda C. Mocuta ,  Dan M. Mocuta

    IPC分类号： H01L29/737

    CPC分类号： H01L29/7842 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/105 ,  H01L29/1608 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

    摘要： The present invention comprises a method for forming a semiconducting device including the steps of providing a layered structure including a substrate, a low diffusivity layer of a first-conductivity dopant; and a channel layer; forming a gate stack atop a protected surface of the channel layer; etching the layered structure selective to the gate stack to expose a surface of the substrate, where a remaining portion of the low diffusivity layer provides a retrograded island substantially aligned to the gate stack having a first dopant concentration to reduce short-channel effects without increasing leakage; growing a Si-containing material atop the recessed surface of the substrate; and doping the Si-containing material with a second-conductivity dopant at a second dopant concentration. The low diffusivity layer may be Si1-x-yGexZy, where Z can be carbon (C), xenon (Xe), germanium (Ge), krypton (Kr), argon (Ar), nitrogen (N), or combinations thereof.

    摘要翻译： 本发明包括一种形成半导体器件的方法，包括以下步骤：提供包括衬底，第一导电掺杂剂的低扩散层的分层结构; 和通道层; 在沟道层的受保护表面上方形成栅极堆叠; 蚀刻对栅极堆叠选择性的层状结构以暴露衬底的表面，其中低扩散层的剩余部分提供基本上与具有第一掺杂剂浓度的栅极堆叠对准的退化岛，以减少短沟道效应而不增加泄漏 ; 在衬底的凹陷表面的顶部生长含Si材料; 并且以第二掺杂剂浓度用第二导电掺杂剂掺杂含Si材料。 低扩散性层可以是Si1-x-yGexZy，其中Z可以是碳（C），氙（Xe），锗（Ge），氪（Kr），氩（Ar），氮（N）或它们的组合。