公开(公告)号：US06555430B1

公开(公告)日：2003-04-29

申请号：US09723420

申请日：2000-11-28

申请人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

发明人： Michael P. Chudzik ,  Johnathan Faltermeier ,  Rajarao Jammy ,  Stephan Kudelka ,  Irene McStay ,  Kenneth T. Settlemyer, Jr. ,  Helmut Horst Tews

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L28/84 ,  Y10S438/964

摘要： Methods forming a trench region of a trench capacitor structure having increase surface area are provided. One method includes the steps of forming a discontinuous polysilicon layer on exposed walls of a lower trench region, the discontinuous polysilicon layer having gaps therein which expose portions of said substrate; oxidizing the lower trench region such that the exposed portions of said substrate provided by the gaps in the discontinuous polysilicon layer are oxidized into oxide material which forms a smooth and wavy layer with the discontinuous polysilicon layer; and etching said oxide material so as to form smooth hemispherical grooves on the walls of the trench region.

摘要翻译： 提供了形成具有增加的表面积的沟槽电容器结构的沟槽区域的方法。 一种方法包括以下步骤：在下沟槽区域的暴露的壁上形成不连续的多晶硅层，所述不连续的多晶硅层在其中具有暴露所述衬底的部分的间隙; 氧化下沟槽区域，使得由不连续多晶硅层中的间隙提供的所述衬底的暴露部分被氧化成与不连续的多晶硅层形成平滑波浪层的氧化物材料; 并蚀刻所述氧化物材料，以在沟槽区域的壁上形成平滑的半球状凹槽。

公开(公告)号：US06458647B1

公开(公告)日：2002-10-01

申请号：US09940761

申请日：2001-08-27

申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Irene McStay

发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Irene McStay

IPC分类号： H01L218242

CPC分类号： H01L29/66181 ,  H01L27/1087 ,  H01L27/11507

摘要： A process for forming a sacrificial collar (116) on the top portion of a deep trench (114). A nitride layer (116) is deposited within the trench (114). A semiconductor layer (120) is deposited over the nitride layer (116). A top portion of the semiconductor layer (120) is doped to form doped semiconductor layer (124). Undoped portions (120) of the semiconductor layer are removed, and the doped semiconductor layer (124) is used to pattern the nitride layer (116), removing the lower portion of nitride layer (116) from within deep trenches (114) and leaving a sacrificial collar (116) at the top of the trenches (114).

摘要翻译： 一种用于在深沟槽（114）的顶部上形成牺牲套环（116）的工艺。 氮化物层（116）沉积在沟槽（114）内。 半导体层（120）沉积在氮化物层（116）上。 掺杂半导体层（120）的顶部以形成掺杂半导体层（124）。 去除半导体层的未掺杂部分（120），并且使用掺杂半导体层（124）对氮化物层（116）进行图案化，从深沟槽（114）中去除氮化物层（116）的下部并离开 在所述沟槽（114）的顶部处的牺牲套环（116）。

公开(公告)号：US06613642B2

公开(公告)日：2003-09-02

申请号：US10016075

申请日：2001-12-13

申请人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

发明人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L28/90

摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

摘要翻译： 公开了一种用于增加半导体器件中原始表面的表面积的方法。 在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。 然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。 因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

公开(公告)号：US06559002B1

公开(公告)日：2003-05-06

申请号：US10032041

申请日：2001-12-31

申请人： Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

发明人： Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L28/84 ,  Y10S438/964

摘要： In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.

摘要翻译： 在制造DT DRAM结构的过程中，提高在轴环区域之下提供的表面积增强的DT和不随着降低的底层/单元尺寸而缩小的节点电容，包括：a）提供具有轴环区域和 在轴环区域下方的相邻区域，其上沉积有SiO的轴环区域; b）在所述轴环区域和轴环下方的区域上沉积SiN衬垫; c）在SiN衬套上沉积a-Si层以形成 微型掩模; d）使所述步骤c）的结构在潮湿环境下在足够的温度下进行退火/氧化步骤，以形成多个氧化物点硬掩模; e）使所述SiN衬底对SiO选择性蚀刻; f） 使用对SiO选择性的化学干蚀刻（CDE）来产生粗糙的Si表面的步骤e）到Si转移蚀刻的结构; g）剥离SiO和SiN; 并形成一个节点和项圈沉积。

公开(公告)号：US06905944B2

公开(公告)日：2005-06-14

申请号：US10249798

申请日：2003-05-08

申请人： Michael Patrick Chudzik ,  Irene McStay ,  Helmut Horst Tews ,  Porshia Shane Wrschka

发明人： Michael Patrick Chudzik ,  Irene McStay ,  Helmut Horst Tews ,  Porshia Shane Wrschka

IPC分类号： H01L21/76 ,  H01L21/8242

CPC分类号： H01L27/1087

摘要： A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench. The oxide layer and the nitride layer is then removed from the lower portion. Finally, the lower portion of the trench is processed selectively to nitride, e.g. by one or more capacitor forming processes, and then the upper portion of the trench is processed.

摘要翻译： 通过本发明提供了蚀刻成半导体衬底的深沟槽的制造方法。 沟槽被分成上部和下部，并且该方法允许下部被加工成与上部不同。 在沟槽被蚀刻到半导体衬底中之后，在沟槽的侧壁上形成氮化物层。 然后在氮化物层上形成一层氧化物。 然后将填料材料沉积并凹入以覆盖沟槽下部的氧化物层，然后从填料材料上方的沟槽上部除去氧化物层。 一旦从沟槽的上部去除氧化物层，也可以去除填充材料，同时允许氧化物层和氮化物层保留在沟槽的下部。 选择性地将硅沉积在沟槽上部的暴露的氮化物层上。 然后从下部去除氧化物层和氮化物层。 最后，沟槽的下部被选择性地加工成氮化物，例如。 通过一个或多个电容器形成工艺，然后处理沟槽的上部。

公开(公告)号：US06620724B1

公开(公告)日：2003-09-16

申请号：US10142518

申请日：2002-05-09

申请人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

发明人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

IPC分类号： H01L214763

CPC分类号： H01L28/60 ,  H01L27/10861

摘要： Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

摘要翻译： 提供其具有低电阻率的具有低填充材料的深沟槽的半导体器件以及制造这种半导体器件的方法。

公开(公告)号：US07157328B2

公开(公告)日：2007-01-02

申请号：US11047312

申请日：2005-01-31

申请人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

发明人： Helmut Horst Tews ,  Stephan Kudelka ,  Kenneth T. Settlemyer

IPC分类号： H01L21/8242

CPC分类号： H01L21/30604 ,  H01L29/66181

摘要： The surface area of the walls of a trench formed in a substrate is increased. A barrier layer is formed on the walls of the trench such that the barrier layer is thinner near the corners of the trench and is thicker between the corners of the trench. A dopant is introduced into the substrate through the barrier layer to form higher doped regions in the substrate near the corners of the trench and lesser doped regions between the corners of the trench. The barrier layer is removed, and the walls of the trench are etched in a manner that etches the lesser doped regions of the substrate at a higher rate than the higher doped regions of the substrate to widen and lengthen the trench and to form rounded corners at the intersections of the walls of the trench.

摘要翻译： 在衬底中形成的沟槽的壁的表面积增加。 阻挡层形成在沟槽的壁上，使得阻挡层在沟槽的角部附近更薄，并且在沟槽的角部之间更厚。 通过势垒层将掺杂剂引入到衬底中，以在衬底附近的沟槽的角部附近形成更高的掺杂区域，并且在沟槽的角部之间形成较小的掺杂区域。 去除阻挡层，并且以如下方式蚀刻沟槽的壁，该方式是以比衬底的较高掺杂区域更高的速率蚀刻衬底的较小掺杂区域，以加宽和延长沟槽并且形成圆角 沟渠墙壁的交叉点。

公开(公告)号：US06677197B2

公开(公告)日：2004-01-13

申请号：US10032040

申请日：2001-12-31

申请人： Stephan Kudelka ,  Helmut Horst Tews

发明人： Stephan Kudelka ,  Helmut Horst Tews

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L29/66181

摘要： In a process for preparing a DT DRAM for sub 100 nm groundrules that normally require the formation of a collar after the bottle formation, the improvement of providing a collar first scheme by forming a high aspect ration PBL SiN barrier, comprising: a) providing a semiconductor structure after SiN node deposition and DT polysilicon fill; b) depositing a poly buffered LOCOS (PBL) Si liner; c) subjecting the PBL liner to oxidation to form a pad oxide and depositing a SiN barrier layer; d) depositing a silicon mask liner; e) subjecting the DT to high directional ion implantation (I/I) using a p-dopant; f) employing a selective wet etch of unimplanted Si with an etch stop on SiN; g) subjecting the product of step f) to a SiN wet etch with an etch stop on the pad oxide; h) affecting a Si liner etch with a stop on the pad oxide; i) oxidizing the PBL Si liner and affecting a barrier SiN strip; j) providing a DT polysilicon fill and performing a poly chemical mechanical polishing.

摘要翻译： 在制备通常需要在瓶形成后形成套环的亚100nm研磨剂制备DT DRAM的方法中，通过形成高面积比PBL SiN阻挡层来改进提供轴环第一方案，该方法包括：a） 在SiN结点沉积和DT多晶硅填充之后的半导体结构; b）沉积多层缓冲LOCOS（PBL）Si衬垫; c）使PBL衬里氧化形成衬垫氧化物并沉积SiN阻挡层; d）沉积硅掩模 衬垫; e）使用p-掺杂剂对DT进行高定向离子注入（I / I）; f）使用SiN上的蚀刻停止对未被注入的Si的选择性湿蚀刻; g）使步骤f）的产物 在衬垫氧化物上具有蚀刻停止层的SiN湿蚀刻; h）影响衬垫氧化物上的停止的Si衬层蚀刻; i）氧化PBL Si衬垫并影响势垒SiN条; j）提供DT多晶硅填充物 进行多化学机械抛光。

公开(公告)号：US06426253B1

公开(公告)日：2002-07-30

申请号：US09576465

申请日：2000-05-23

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Brian S. Lee ,  Uwe Schroeder ,  Stephan Kudelka

IPC分类号： H01L218242

CPC分类号： H01L27/10864 ,  H01L21/76237 ,  H01L21/823487 ,  H01L27/10841 ,  H01L27/10867

摘要： A system and method of forming an electrical connection (142) to the interior of a deep trench (104) in an integrated circuit utilizing a low-angle dopant implantation (114) to create a self-aligned mask over the trench. The electrical connection preferably connects the interior plate (110) of a trench capacitor to a terminal of a vertical trench transistor. The low-angle implantation process, in combination with a low-aspect ratio mask structure, generally enables the doping of only a portion of a material overlying or in the trench. The material may then be subjected to a process step, such as oxidation, with selectivity between the doped and undoped regions. Another process step, such as an etch process, may then be used to remove a portion of the material (120) overlying or in the trench, leaving a self-aligned mask (122) covering a portion of the trench, and the remainder of the trench exposed for further processing. Alternatively, an etch process alone, with selectivity between the doped and undoped regions, may be used to create the mask. The self-aligned mask then allows for the removal of selective portions of the materials in the trench so that a vertical trench transistor and a buried strap may be formed on only one side of the trench.

摘要翻译： 使用低角度掺杂剂注入（114）在集成电路中形成到深沟槽（104）的内部的电连接（142）的系统和方法，以在沟槽上产生自对准掩模。 电连接优选地将沟槽电容器的内板（110）连接到垂直沟槽晶体管的端子。 低角度注入工艺与低纵横比掩模结构相结合，通常能够仅掺杂覆盖或在沟槽中的材料的一部分。 然后可以在掺杂区域和未掺杂区域之间选择性地对材料进行处理步骤，例如氧化。 然后可以使用诸如蚀刻工艺的另一工艺步骤来去除覆盖在沟槽中或在沟槽中的部分材料（120），留下覆盖沟槽的一部分的自对准掩模（122），并且其余部分 沟槽暴露进一步加工。 或者，可以使用仅在掺杂区域和未掺杂区域之间具有选择性的蚀刻工艺来产生掩模。 自对准掩模然后允许去除沟槽中的材料的选择性部分，使得可以仅在沟槽的一侧上形成垂直沟槽晶体管和掩埋带。

公开(公告)号：US06335247B1

公开(公告)日：2002-01-01

申请号：US09597389

申请日：2000-06-19

申请人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

发明人： Helmut Horst Tews ,  Alexander Michaelis ,  Stephan Kudelka ,  Uwe Schroeder ,  Brian S. Lee

IPC分类号： H01L21336

CPC分类号： H01L27/10864 ,  H01L27/10876

摘要： A method of forming a vertically-oriented device in an integrated circuit using a selective wet etch to remove only a part of the sidewalls in a deep trench, and the device formed therefrom. While a portion of the trench perimeter (e.g., isolation collar 304) is protected by a mask (e.g., polysilicon 318), the exposed portion is selectively wet etched to remove selected crystal planes from the exposed portion of the trench, leaving a flat substrate sidewall (324) with a single crystal plane. A single side vertical trench transistor may be formed on the flat sidewall. A vertical gate oxide (e.g. silicon dioxide 330) of the transistor formed on the single crystal plane is substantially uniform across the transistor channel, providing reduced chance of leakage and consistent threshold voltages from device to device. In addition, trench widening is substantially reduced, increasing the device to device isolation distance in a single sided buried strap junction device layout.

摘要翻译： 一种使用选择性湿蚀刻在集成电路中形成垂直取向器件的方法，以仅去除深沟槽中的一部分侧壁，以及由此形成的器件。 虽然沟槽周边的一部分（例如，隔离环304）被掩模（例如，多晶硅318）保护，但是暴露部分被选择性地湿蚀刻以从沟槽的暴露部分移除所选择的晶面，留下平坦的衬底 侧壁（324）与单晶面。 单侧垂直沟槽晶体管可以形成在平坦侧壁上。 形成在单晶平面上的晶体管的垂直栅极氧化物（例如二氧化硅330）在晶体管沟道上基本上是均匀的，从而降低了泄漏的机会和从器件到器件的一致的阈值电压。 此外，沟槽加宽大大降低，从而在单面掩埋带接合器件布局中将器件增加到器件隔离距离。