公开(公告)号：US4389257A

公开(公告)日：1983-06-21

申请号：US288608

申请日：1981-07-30

申请人： Henry J. Geipel, Jr. ,  Ning Hsieh ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Henry J. Geipel, Jr. ,  Ning Hsieh ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L21/285

CPC分类号： H01L29/4975 ,  H01L21/28061 ,  H01L21/321 ,  H01L21/76889 ,  Y10S148/147

摘要： A method of providing self-passivating interconnection electrodes for semiconductor devices which provides low resistivity composite polysiliconsilicide electrodes. In the method the formation of oxidation induced voids in polysilicon underlying the silicide is eliminated by deposition of polysilicon and stoichiometric proportions of silicon and a silicide-forming metal. These steps are followed by deposition of a silicon layer having a thickness determined to provide between 30 and 100 percent of the silicon required to form a silicon dioxide passivation layer. Subsequent thermal oxidation of the layered electrode structure provides a self-passivated structure useful for fabrication of silicon gate MOSFET devices as well as other integrated circuit structures.

摘要翻译： 一种提供半导体器件的自钝化互连电极的方法，其提供低电阻率复合多硅化物电极。 在该方法中，通过沉积多晶硅和化学计量比例的硅和形成硅化物的金属来消除在硅化物下面的多晶硅中形成氧化诱发的空隙。 这些步骤之后是沉积具有确定提供形成二氧化硅钝化层所需的硅的30％至100％的厚度的硅层。 层状电极结构的随后的热氧化提供了用于制造硅栅极MOSFET器件以及其它集成电路结构的自钝化结构。

公开(公告)号：US07393779B2

公开(公告)日：2008-07-01

申请号：US11163786

申请日：2005-10-31

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L21/4763

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144

摘要： Sublithographic contact apertures through a dielectric are formed in a stack of dielectric, hardmask and oxide-containing seed layer. An initial aperture through the seed layer receives a deposition of oxide by liquid phase deposition, which adheres selectively to the exposed vertical walls of the aperture in the seed layer. The sublithographic aperture, reduced in size by the thickness of the added material, defines a reduced aperture in the hardmask. The reduced hardmask then defines the sublithographic aperture through the dielectric.

摘要翻译： 通过电介质的亚光刻接触孔形成在电介质，硬掩模和含氧化物种子层的堆叠中。 通过种子层的初始孔径通过液相沉积接收氧化物沉积，该相沉积选择性地粘附到种子层中的孔的暴露的垂直壁。 通过所添加的材料的厚度减小尺寸的亚光刻孔径在硬掩模中限定了减小的孔径。 缩小的硬掩模然后限定通过电介质的亚光刻孔。

公开(公告)号：US07250347B2

公开(公告)日：2007-07-31

申请号：US10905979

申请日：2005-01-28

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit

IPC分类号： H01L21/336

CPC分类号： H01L29/66772 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/78654

摘要： A method for forming transistors with mutually-aligned double gates. The method includes the steps of (a) providing a wrap-around-gate transistor structure, wherein the wrap-around-gate transistor structure includes (i) semiconductor region, and (ii) a gate electrode region wrapping around the semiconductor region, wherein the gate electrode region is electrically insulated from the semiconductor region by a gate dielectric film; and (b) removing first and second portions of the wrap-around-gate transistor structure so as to form top and bottom gate electrodes from the gate electrode region, wherein the top and bottom gate electrodes are electrically disconnected from each other.

摘要翻译： 一种用于形成具有相互对准的双栅极的晶体管的方法。 该方法包括以下步骤：（a）提供环绕栅极晶体管结构，其中环绕栅极晶体管结构包括（i）半导体区域和（ii）围绕半导体区域包围的栅电极区域，其中 栅电极区域通过栅极电介质膜与半导体区域电绝缘; 以及（b）去除环绕栅极晶体管结构的第一和第二部分，以便从栅极电极区域形成顶部和底部栅电极，其中顶部和底部栅电极彼此电断开。

公开(公告)号：US20090014767A1

公开(公告)日：2009-01-15

申请号：US10596022

申请日：2003-12-18

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L27/108

CPC分类号： H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

摘要： A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

摘要翻译： 沟槽式存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成在沟槽内衬的开放圆筒结构。 该器件通过在衬底上提供碳纳米管催化剂结构并对衬底中的沟槽进行图案化而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

公开(公告)号：US4558508A

公开(公告)日：1985-12-17

申请号：US660673

申请日：1984-10-15

申请人： Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

发明人： Wayne I. Kinney ,  Charles W. Koburger, III ,  Jerome B. Lasky ,  Larry A. Nesbit ,  Ronald R. Troutman ,  Francis R. White

IPC分类号： H01L27/08 ,  H01L21/033 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L29/78

CPC分类号： H01L21/76218 ,  H01L21/033 ,  H01L21/823892 ,  H01L29/0638 ,  H01L27/0928 ,  Y10S148/043 ,  Y10S148/053 ,  Y10S148/10 ,  Y10S148/157

摘要： A process for making a CMOS dual-well semiconductor structure with field isolation doping, wherein only a single lithographic masking step is required for providing self-alignment both of the wells to each other and also of the field isolation doping regions to the wells. The lithographic masking step forms a well mask and defines an oxidation barrier which acts as: an implant mask (absorber) during the ion-implantation of a field dopant of one type; an oxidation barrier over one well during the oxidation of the opposite-type well to form over the one well a sacrificial oxide layer which forms the alignment marks for subsequent formation of the field-doping regions; and a dopant-transmitter during the ion-implantation of an opposite-type field dopant which is simultaneously absorbed by the sacrificial oxide. As a result, there are formed field-doped oxide layers self-aligned to the wells so that, with a subsequent masking step, oxide field isolations are defined over the doped oxide layers. A heat cycle is then used to drive the field dopants into the corresponding field-doping regions.

摘要翻译： 制造具有场隔离掺杂的CMOS双阱半导体结构的方法，其中仅需要单个光刻掩模步骤，以提供阱彼此之间的自对准以及对阱的场隔离掺杂区域的自对准。 光刻掩模步骤形成了良好的掩模，并且限定了一种氧化屏障，其作用为在一种类型的场掺杂剂的离子注入期间的注入掩模（吸收体） 在相对孔的氧化期间在一个阱上形成氧化屏障，以在一个阱上形成牺牲氧化物层，其形成用于随后形成场掺杂区域的对准标记; 以及在由牺牲氧化物同时吸收的相反型场掺杂剂的离子注入期间的掺杂剂发射器。 结果，形成了与阱自对准的场掺杂氧化物层，使得通过随后的掩模步骤，在掺杂的氧化物层上限定氧化物场隔离。 然后使用热循环将场掺杂剂驱动到相应的场掺杂区域中。

公开(公告)号：US07932549B2

公开(公告)日：2011-04-26

申请号：US10596022

申请日：2003-12-18

申请人： Steven J. Holmes ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Steven J. Holmes ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L27/108

CPC分类号： H01L27/10864 ,  B82Y10/00 ,  H01L27/10861 ,  Y10S977/936 ,  Y10S977/943 ,  Y10S977/948

摘要： A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.

摘要翻译： 沟槽式存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。 可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。 碳纳米管束形成在沟槽内衬的开放圆筒结构。 该器件通过在衬底上提供碳纳米管催化剂结构并对衬底中的沟槽进行图案化而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

公开(公告)号：US07585614B2

公开(公告)日：2009-09-08

申请号：US10711458

申请日：2004-09-20

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

IPC分类号： G03F7/00

CPC分类号： H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139

摘要： A method of patterning which provides images substantially smaller than that possible by lithographic techniques is provided. In the method of the invention, a substrate has a memory layer and a sacrificial layer formed thereon. An image is patterned onto the memory layer by protecting an edge during an etching step using chemical oxide removal (COR) processes, for example. Another edge is memorized in the layer. The sacrificial layer is removed to expose another memorized edge, which is used to define a pattern in an underlying layer.

摘要翻译： 提供了一种通过光刻技术提供显着小于可能的图像的图案化方法。 在本发明的方法中，衬底具有形成在其上的存储层和牺牲层。 例如，通过使用化学氧化物去除（COR）工艺在蚀刻步骤期间保护边缘，将图像图案化到存储层上。 另一个边缘被记住在图层中。 去除牺牲层以露出另一个存储的边缘，其用于在下层中定义图案。

公开(公告)号：US06875685B1

公开(公告)日：2005-04-05

申请号：US10605766

申请日：2003-10-24

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Peter H. Mitchell ,  Larry A. Nesbit ,  James A. Slinkman

IPC分类号： H01L21/4763 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L29/40

CPC分类号： H01L21/7682 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a gas dielectric with support structure on a semiconductor device structure provides low capacitance and adequate support for a conductor of the semiconductor device structure. A conductive structure, such as via or interconnect, is formed in a wing-layer dielectric. A support is then formed that connects to the conductive structure, the support including an area thereunder. The wiring-layer dielectric is then removed from the area to form a gas dielectric.

摘要翻译： 在半导体器件结构上形成具有支撑结构的气体电介质的方法为半导体器件结构的导体提供低电容和足够的支撑。 在翼层电介质中形成诸如通孔或互连的导电结构。 然后形成连接到导电结构的支撑件，支撑件包括其下的区域。 然后从该区域去除布线层电介质以形成气体电介质。

公开(公告)号：US07504314B2

公开(公告)日：2009-03-17

申请号：US10907565

申请日：2005-04-06

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L29/93 ,  H01L21/76

CPC分类号： H01L21/76267 ,  H01L21/76243 ,  H01L21/76281 ,  H01L21/76283

摘要： The invention relates generally to a method for fabricating oxygen-implanted semiconductors, and more particularly to a method for fabricating oxygen-implanted silicon-on-insulation (“SOI”) type semiconductors by cutting-up regions into device-sized pieces prior to the SOI-oxidation process. The process sequence to make SOI is modified so that the implant dose may be reduced and relatively long and high temperature annealing process steps may be shortened or eliminated. This simplification may be achieved if, after oxygen implant, the wafer structure is sent to pad formation, and masking and etching. After the etching, annealing or oxidation process steps may be performed to create the SOI wafer.

摘要翻译： 本发明一般涉及一种用于制造氧注入半导体的方法，更具体地说，涉及一种用于将氧注入的硅绝缘（“SOI”）型半导体通过切割区域制造成器件尺寸的片之前的方法 SOI氧化工艺。 制造SOI的工艺顺序被修改，使得可以减少注入剂量并且相对较长并且可以缩短或消除高温退火工艺步骤。 如果在氧注入之后将晶片结构发送到焊盘形成以及掩模和蚀刻，则可以实现这种简化。 在蚀刻之后，可以执行退火或氧化工艺步骤以产生SOI晶片。

公开(公告)号：US07256114B2

公开(公告)日：2007-08-14

申请号：US10905881

申请日：2005-01-25

申请人： Steven J. Holmes ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

发明人： Steven J. Holmes ,  Toshiharu Furukawa ,  Mark C. Hakey ,  David V. Horak ,  Charles W. Koburger, III ,  Larry A. Nesbit

IPC分类号： H01L21/00

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/3165 ,  H01L21/76829 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10888

摘要： A process for forming a semiconductor device having an oxide beanie structure (an oxide cap overhanging an underlying portion of the device). An oxide layer is first provided covering that portion, with the layer having a top surface and a side surface. The top and side surfaces are then exposed to an oxide deposition bath, thereby causing deposition of oxide on those surfaces. Deposition of oxide on the top surface causes growth of the cap layer in a vertical direction and deposition of oxide on the side surface causes growth of the cap layer in a horizontal direction, thereby forming the beanie structure.

摘要翻译： 一种用于形成具有氧化物结构的氧化物半导体器件的方法（在器件的下面突出的氧化物盖）。 首先设置覆盖该部分的氧化物层，该层具有顶表面和侧表面。 然后将顶表面和侧表面暴露于氧化物沉积浴中，从而在这些表面上沉积氧化物。 顶部表面上的氧化物的沉积导致盖层在垂直方向上的生长，并且在侧面上的氧化物的沉积导致盖层在水平方向上的生长，从而形成豆瓣结构。