公开(公告)号：US20130113068A1

公开(公告)日：2013-05-09

申请号：US13588438

申请日：2012-08-17

申请人： Vidhya Ramachandran ,  Shiqun Gu

发明人： Vidhya Ramachandran ,  Shiqun Gu

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.

摘要翻译： 低K值介电保护间隔物，用于通过低K值布线层通过衬底通孔（TSV）进行构图。 形成低K值介电保护间隔物的方法包括通过低K值电介质互连层蚀刻通孔。 保护层沉积在通孔开口和低K值电介质互连层上。 保护层的至少一部分从通孔开口的底部和低K值电介质互连层的水平表面被蚀刻。 蚀刻在通孔开口的侧壁上留下保护性侧壁间隔物。 穿通基板通孔被蚀刻穿过通孔开口的底部并穿过半导体基板。 直通基板通孔用导电材料填充。

公开(公告)号：US08779559B2

公开(公告)日：2014-07-15

申请号：US13405600

申请日：2012-02-27

申请人： Vidhya Ramachandran ,  Shiqun Gu

发明人： Vidhya Ramachandran ,  Shiqun Gu

IPC分类号： H01L23/522

CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face. The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion.

摘要翻译： 包括通过衬底通孔（TSV）的应变消除的半导体管芯。 半导体管芯包括具有主动面的半导体衬底。 半导体衬底包括连接到有源面的导电层。 半导体管芯还包括仅通过衬底延伸的贯通衬底。 直通衬底通孔可以包括通过穿过衬底通孔的长度的基本上恒定的直径。 贯通基板通孔可以填充有导电填充材料。 半导体管芯还包括围绕贯穿衬底通孔的隔离层。 隔离层可以包括两部分：靠近衬底的有源面的凹陷部分，其能够缓和来自导电填充材料的应力，以及介电部分。 凹部的组成可以不同于电介质部分。

公开(公告)号：US20130221494A1

公开(公告)日：2013-08-29

申请号：US13405600

申请日：2012-02-27

申请人： Vidhya Ramachandran ,  Shiqun Gu

发明人： Vidhya Ramachandran ,  Shiqun Gu

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76898 ,  H01L21/7682 ,  H01L21/76831 ,  H01L23/481 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor die including strain relief for through substrate vias (TSVs). The semiconductor die includes a semiconductor substrate having an active face. The semiconductor substrate includes conductive layers connected to the active face, The semiconductor die also includes a through substrate via extending only through the substrate. The through substrate via may include a substantially constant diameter through a length of the through substrate via. The through substrate via may be filled with a conductive filler material. The semiconductor die also includes an isolation layer surrounding the through substrate via. The isolation layer may include two portions: a recessed portion near the active face of the substrate capable of relieving stress from the conductive filler material, and a dielectric portion. A composition of the recessed portion may differ from the dielectric portion.

摘要翻译： 包括通过衬底通孔（TSV）的应变消除的半导体管芯。 半导体管芯包括具有主动面的半导体衬底。 半导体衬底包括连接到有源面的导电层。半导体管芯还包括仅通过衬底延伸的穿通衬底。 直通衬底通孔可以包括通过穿过衬底通孔的长度的基本上恒定的直径。 贯通基板通孔可以填充有导电填充材料。 半导体管芯还包括围绕贯穿衬底通孔的隔离层。 隔离层可以包括两部分：靠近衬底的有源面的凹陷部分，其能够缓和来自导电填充材料的应力，以及介电部分。 凹部的组成可以不同于电介质部分。

公开(公告)号：US09059263B2

公开(公告)日：2015-06-16

申请号：US13588438

申请日：2012-08-17

申请人： Vidhya Ramachandran ,  Shiqun Gu

发明人： Vidhya Ramachandran ,  Shiqun Gu

IPC分类号： H01L21/338 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low-K value dielectric protection spacer for patterning through substrate vias (TSVs) through a low-K value wiring layer. A method for forming a low-K value dielectric protection spacer includes etching a via opening through a low-K value dielectric interconnect layer. A protective layer is deposited in the via opening and on the low-K value dielectric interconnect layer. At least a portion of the protective layer is etched from the bottom of the via opening and from a horizontal surface of the low-K value dielectric interconnect layer. The etching leaving a protective sidewall spacer on a sidewall of the via opening. A through substrate via is etched through the bottom of the via opening and through the semiconductor substrate. The through substrate via is filled with a conductive material.

摘要翻译： 低K值介电保护间隔物，用于通过低K值布线层通过衬底通孔（TSV）进行构图。 形成低K值介电保护间隔物的方法包括通过低K值电介质互连层蚀刻通孔。 保护层沉积在通孔开口和低K值电介质互连层上。 保护层的至少一部分从通孔开口的底部和低K值电介质互连层的水平表面被蚀刻。 蚀刻在通孔开口的侧壁上留下保护性侧壁间隔物。 穿通基板通孔被蚀刻穿过通孔开口的底部并穿过半导体基板。 直通基板通孔用导电材料填充。

公开(公告)号：US07825019B2

公开(公告)日：2010-11-02

申请号：US11863724

申请日：2007-09-28

申请人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

发明人： Lawrence A. Clevenger ,  Stephan Grunow ,  Kaushik A. Kumar ,  Kevin Shawn Petrarca ,  Vidhya Ramachandran

IPC分类号： H01L21/44

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L21/76829 ,  H01L23/522 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S438/926 ,  Y10S438/928 ,  H01L2924/00

摘要： A semiconductor structure and a method for forming the same. The structure includes (a) a substrate which includes semiconductor devices and (b) a first ILD (inter-level dielectric) layer on top of the substrate. The structure further includes N first actual metal lines in the first ILD layer, N being a positive integer. The N first actual metal lines are electrically connected to the semiconductor devices. The structure further includes first trenches in the first ILD layer. The first trenches are not completely filled with solid materials. If the first trenches are completely filled with first dummy metal lines, then (i) the first dummy metal lines are not electrically connected to any semiconductor device and (ii) the N first actual metal lines and the first dummy metal lines provide an essentially uniform pattern density of metal lines across the first ILD layer.

摘要翻译： 半导体结构及其形成方法。 该结构包括（a）包括半导体器件的衬底和（b）在衬底顶部上的第一ILD（层间电介质）层。 该结构还包括第一ILD层中的N个第一实际金属线，N是正整数。 N个第一实际金属线电连接到半导体器件。 该结构还包括第一ILD层中的第一沟槽。 第一条沟没有完全填满固体材料。 如果第一沟槽被完全填充第一虚拟金属线，则（i）第一虚设金属线不与任何半导体器件电连接，并且（ii）N个第一实际金属线和第一虚拟金属线提供基本均匀的 跨越第一ILD层的金属线的图案密度。

公开(公告)号：US20090039522A1

公开(公告)日：2009-02-12

申请号：US10596573

申请日：2003-12-16

申请人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

发明人： Zhong-Xiang He ,  Bradley A. Orner ,  Vidhya Ramachandran ,  Alvin J. Joseph ,  Stephen A. St. Onge ,  Ping-Chuan Wang

IPC分类号： H01L23/52

CPC分类号： H01L21/76838 ,  H01L21/76802 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/5389 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a method and structure for an integrated circuit structure that includes a plurality of complementary metal oxide semiconductor (CMOS) transistors and a plurality of vertical bipolar transistors positioned on a single substrate. The vertical bipolar transistors are taller devices than the CMOS transistors. In this structure, a passivating layer is positioned above the substrate, and between the vertical bipolar transistors and the CMOS transistors. A wiring layer is above the passivating layer. The vertical bipolar transistors are in direct contact with the wiring layer and the CMOS transistors are connected to the wiring layer by contacts extending through the passivating layer.

摘要翻译： 公开了一种集成电路结构的方法和结构，其包括多个互补金属氧化物半导体（CMOS）晶体管和位于单个衬底上的多个垂直双极晶体管。 垂直双极晶体管比CMOS晶体管更高的器件。 在该结构中，钝化层位于衬底上方，并且位于垂直双极晶体管和CMOS晶体管之间。 布线层位于钝化层的上方。 垂直双极晶体管与布线层直接接触，并且CMOS晶体管通过延伸穿过钝化层的触点连接到布线层。

公开(公告)号：US07473979B2

公开(公告)日：2009-01-06

申请号：US11443394

申请日：2006-05-30

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L29/92

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。

公开(公告)号：US20070063244A1

公开(公告)日：2007-03-22

申请号：US11162776

申请日：2005-09-22

申请人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

发明人： Herbert Ho ,  Subramanian Iyer ,  Vidhya Ramachandran

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/10867 ,  H01L27/1087 ,  H01L27/1203

摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET). The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体 - 金属（MIM）电容器和场效应晶体管（FET）的半导体器件。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

公开(公告)号：US07750388B2

公开(公告)日：2010-07-06

申请号：US11961076

申请日：2007-12-20

申请人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

发明人： Herbert L. Ho ,  Subramanian S. Iyer ,  Vidhya Ramachandran

IPC分类号： H01L31/062 ,  H01L29/94 ,  G06F9/45

CPC分类号： H01L28/91 ,  H01L27/10861

摘要： The present invention relates to a semiconductor device that contains a trench metal-insulator-metal (MIM) capacitor and a field effect transistor (FET), and a design structure including the semiconductor device embodied in a machine readable medium. The trench MIM capacitor comprises a first metallic electrode layer located over interior walls of a trench in a substrate, a dielectric layer located in the trench over the first metallic electrode layer, and a second metallic electrode layer located in the trench over the dielectric layer. The FET comprises a source region, a drain region, a channel region between the source and drain regions, and a gate electrode over the channel region. The trench MIM capacitor is connected to the FET by a metallic strap. The semiconductor device of the present invention can be fabricated by a process in which the trench MIM capacitor is formed after the FET source/drain region but before the FET source/drain metal silicide contacts, for minimizing metal contamination in the FET.

摘要翻译： 本发明涉及一种包含沟槽金属 - 绝缘体金属（MIM）电容器和场效应晶体管（FET）的半导体器件，以及包括体现在机器可读介质中的半导体器件的设计结构。 沟槽MIM电容器包括位于衬底中的沟槽的内壁上方的第一金属电极层，位于第一金属电极层上的沟槽中的电介质层和位于电介质层上的沟槽中的第二金属电极层。 FET包括源极区域，漏极区域，源极和漏极区域之间的沟道区域以及沟道区域上的栅极电极。 沟槽MIM电容器通过金属带连接到FET。 本发明的半导体器件可以通过在FET源极/漏极区域之后但FET源极/漏极金属硅化物接触之前形成沟槽MIM电容器以最小化FET中的金属污染的工艺来制造。

公开(公告)号：US20090111235A1

公开(公告)日：2009-04-30

申请号：US12348707

申请日：2009-01-05

申请人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

发明人： Lawrence Clevenger ,  Timothy Joseph Dalton ,  Louis Hsu ,  Carl Radens ,  Vidhya Ramachandran ,  Keith Kwong Hon Wong ,  Chih-Chao Yang

IPC分类号： H01L21/02

CPC分类号： H01L21/84 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/1203 ,  H01L2924/0002 ,  Y10S438/957 ,  H01L2924/00

摘要： Methods are provided for fabricating semiconductor IC (integrated circuit) chips having high-Q on-chip capacitors formed on the chip back-side and connected to integrated circuits on the chip front-side using through-wafer interconnects. In one aspect, a semiconductor device includes a semiconductor substrate having a front side, a back side, and a buried insulating layer interposed between the front and back sides of the substrate. An integrated circuit is formed on the front side of the semiconductor substrate, an integrated capacitor is formed on the back side of the semiconductor substrate, and an interconnection structure is formed through the buried insulating layer to connect the integrated capacitor to the integrated circuit.

摘要翻译： 提供了用于制造半导体IC（集成电路）芯片的半导体IC（集成电路）芯片，其具有形成在芯片背面的高Q片上电容器，并使用晶片间互连连接到芯片正面的集成电路。 在一个方面，半导体器件包括一个半导体衬底，该半导体衬底具有介于衬底的正面和背面之间的正面，背面和掩埋绝缘层。 在半导体基板的正面形成有集成电路，在半导体基板的背面形成有集成电容器，通过埋入绝缘层形成互连结构，将集成电容器与集成电路连接起来。