公开(公告)号：US5812859A

公开(公告)日：1998-09-22

申请号：US835511

申请日：1997-04-08

申请人： Hideki Kamimaki ,  Koichi Isaji ,  Masatomi Sasaki ,  Koichi Kimura ,  Takayuki Tamura ,  Tsuguji Tachiuchi

发明人： Hideki Kamimaki ,  Koichi Isaji ,  Masatomi Sasaki ,  Koichi Kimura ,  Takayuki Tamura ,  Tsuguji Tachiuchi

IPC分类号： G06F12/16 ,  G06F1/00 ,  G06F1/32 ,  G06F9/445 ,  G06F11/14 ,  G06F1/30

CPC分类号： G06F9/4418

摘要： An information processing apparatus having a work suspend/resume function which allows operator to use a main memory shared by different processings even when work suspension information is saved therein. A system for allowing a same operational environment as that set up in one information processing apparatus to be easily implemented in another information processing apparatus. A main memory used by a CPU for execution of processings has a function for storing information concerning the state of the information processing apparatus prevailing at a time point when execution of a given processing is suspended by a CPU for allowing the suspended processing to be performed in continuation later on. When the suspension state information has already been stored in the main memory by a former user, the suspension state information is transferred to a removable nonvolatile storage device so that the CPU can perform other processing than the suspended one by using the main memory. The transfer of the suspension state information is performed by the CPU.

摘要翻译： 具有工作挂起/恢复功能的信息处理装置，即使在其中保存工作暂停信息时，也允许操作者使用通过不同处理共享的主存储器。 用于允许与在一个信息处理设备中设置的操作环境相同的操作环境的系统可以容易地在另一个信息处理设备中实现。 用于执行处理的CPU使用的主存储器具有用于存储关于在执行给定处理的时间点处的信息处理设备的状态的信息的功能，所述信息处理设备的状态由CPU暂停，以允许执行暂停处理 后续延续。 当暂停状态信息已经由前一个用户存储在主存储器中时，暂停状态信息被传送到可移动非易失性存储设备，使得CPU可以通过使用主存储器执行比暂停状态信息的其他处理。 暂停状态信息的传送由CPU执行。

公开(公告)号：US5867148A

公开(公告)日：1999-02-02

申请号：US912165

申请日：1992-07-10

申请人： Hideki Kamimaki ,  Kiyokazu Nishioka ,  Koichi Kimura ,  Takashi Maruyama ,  Tsuguji Tachiuchi ,  Koichi Isaji ,  Tsuyoshi Nakagawa ,  Nobuo Tsuchiya ,  Yoshiyuki Amano ,  Taisuke Kashima ,  Akira Takahashi ,  Tadashi Kyoda ,  Ryooichi Mizuno

发明人： Hideki Kamimaki ,  Kiyokazu Nishioka ,  Koichi Kimura ,  Takashi Maruyama ,  Tsuguji Tachiuchi ,  Koichi Isaji ,  Tsuyoshi Nakagawa ,  Nobuo Tsuchiya ,  Yoshiyuki Amano ,  Taisuke Kashima ,  Akira Takahashi ,  Tadashi Kyoda ,  Ryooichi Mizuno

IPC分类号： G06F1/16 ,  G06F1/20 ,  G06F3/02 ,  G09G5/00

CPC分类号： G06F1/1616 ,  G06F1/16 ,  G06F1/1669 ,  G06F1/1677 ,  G06F1/1679 ,  G06F1/20 ,  G06F3/0208 ,  G06F2200/1631 ,  Y10S345/905

摘要： An information processing apparatus includes in its body at least a power supply unit, a disk type storage and a printed circuit board arranged in a predetermined order and further has a keyboard unit which can be sandwiched between the display unit and a keyboard unit supporting portion extending from the body by pivotally moving the display unit. A detector for detecting the detachment of the keyboard unit from the body may be provided to restrict the range of pivotal movement of the display unit in accordance with a detection signal of the detector. Further, the display unit may be provided with pilot light emitting portions, thereby making it possible to recognize a condition of the information processing apparatus.

摘要翻译： 一种信息处理装置，其主体至少包括以预定顺序布置的电源单元，盘型存储器和印刷电路板，并且还具有可以夹在显示单元和延伸的键盘单元支撑部分之间的键盘单元 通过枢转地移动显示单元从身体。 可以提供用于检测键盘单元与主体分离的检测器，以根据检测器的检测信号来限制显示单元的枢转​​运动的范围。 此外，显示单元可以设置有引导光发射部分，从而可以识别信息处理设备的状况。

公开(公告)号：US5511201A

公开(公告)日：1996-04-23

申请号：US857629

申请日：1992-03-25

申请人： Hideki Kamimaki ,  Kiyokazu Nishioka ,  Tsuguji Tachiuchi ,  Nobuo Tsuchiya ,  Masahiro Jinushi ,  Hitoshi Sadamitsu ,  Hiroshi Ito ,  Takashi Yoshitomi ,  Koichi Isaji ,  Takao Ohba

发明人： Hideki Kamimaki ,  Kiyokazu Nishioka ,  Tsuguji Tachiuchi ,  Nobuo Tsuchiya ,  Masahiro Jinushi ,  Hitoshi Sadamitsu ,  Hiroshi Ito ,  Takashi Yoshitomi ,  Koichi Isaji ,  Takao Ohba

IPC分类号： G09G3/34 ,  G06F11/00 ,  G06F11/30

CPC分类号： G09G3/3406 ,  G09G2320/0606 ,  G09G2320/0626 ,  G09G2330/021 ,  G09G2330/026

摘要： A data processing apparatus which includes a display unit and a power supply controller for supplying power to the display unit. The display unit has a display screen and a back light controller. The power supply controller comprises a switch, at least one output line for receiving the power from the switch and for supplying therethrough the power to electronic devices, a delay circuit for receiving the power from the switch and when the switch is turned ON to start supply of the power, for outputting the power after passage of a predetermined time from the start of the power supply, and a second output line for supplying the power from the delay circuit to the back light controller therethrough. The display unit has a memory means for storing therein a luminance data on the display screen through the back light controller when the power supply is turned OFF and for determining an output state of the display unit through the back light controller on the basis of the luminance data read out from the memory means when the power supply is turned ON. Further, the data processing apparatus has a means for invalidating output of a display data to be output onto the display screen and a means, after the display data is invalidated, for reducing a frequency of a timing signal or invalidating output of the timing signal for the display unit.

摘要翻译： 一种数据处理装置，包括显示单元和用于向显示单元供电的电源控制器。 显示单元具有显示屏和背光控制器。 电源控制器包括开关，至少一个输出线，用于从开关接收电力并通过其向电子设备提供电力;延迟电路，用于从开关接收电力;以及当开关接通以开始供电时 的功率，用于在从电源开始经过预定时间之后输出电力;以及第二输出线，用于将来自延迟电路的电力提供给背光控制器。 显示单元具有存储装置，用于当电源关闭时通过背光控制器在其上存储亮度数据，并且通过背光控制器基于亮度来确定显示单元的输出状态 当电源接通时，从存储器读出的数据意味着。 此外，数据处理装置具有使输出到显示屏幕上的显示数据的输出无效的装置和在显示数据无效之后的装置，用于减少定时信号的频率或使定时信号的输出无效， 显示单元。

公开(公告)号：US4839739A

公开(公告)日：1989-06-13

申请号：US23262

申请日：1987-03-09

申请人： Tsuguji Tachiuchi ,  Satoshi Konuma ,  Nobuo Tsuchiya

发明人： Tsuguji Tachiuchi ,  Satoshi Konuma ,  Nobuo Tsuchiya

IPC分类号： H04N1/40 ,  H04N1/403

CPC分类号： H04N1/403 ,  H04N1/40056

摘要： A one-dimensional image sensor comprising a solid image pick-up element takes images in sequence, and generates an image signal. Clock pulses from a frequency variable type clock pulse generator having a frequency which varies in correspondence to a control signal are supplied to a one-dimensional image sensor, thereby image signals are outputted in sequence. The image signal is amplified by an amplifier and inputted to a comparator and compared with a reference signal. A frequency variable range of the frequency variable type clock pulse generator is set higher than the cut-off frequency of the amplifier, and the binary level output by the comparator is substantially the same as the image inputted to the one-dimensional image sensor and control is effected by the variable frequency of the clock pulses.

摘要翻译： 包括实心图像拾取元件的一维图像传感器依次拍摄图像并产生图像信号。 来自具有对应于控制信号变化的频率的频率可变型时钟脉冲发生器的时钟脉冲被提供给一维图像传感器，由此依次输出图像信号。 图像信号被放大器放大并输入到比较器并与参考信号进行比较。 频率可变型时钟脉冲发生器的频率可变范围被设置为高于放大器的截止频率，并且由比较器输出的二进制电平基本上与输入到一维图像传感器的图像和控制 受时钟脉冲的可变频率的影响。

公开(公告)号：US4808991A

公开(公告)日：1989-02-28

申请号：US2198

申请日：1987-01-12

申请人： Tsuguji Tachiuchi ,  Hiroyuki Mano ,  Terumi Takashi

发明人： Tsuguji Tachiuchi ,  Hiroyuki Mano ,  Terumi Takashi

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/3611 ,  G09G3/2018

摘要： A liquid crystal display is capable of displaying intermediate, partial or half tones of images, while at the same time preventing the occurrence of flicker and the decay of the liquid crystal panel. The display operation for data to be displayed in an intermediate tone has one or more lines of a repeating frame of display data that are prohibited from being displayed during in each frame. Such inhibited display lines are designated differently on a sequential basis over consecutive frames, and the sequence of designation is varied in successive frames in accord with changing patterns.

摘要翻译： 液晶显示器能够显示中间，部分或半色调的图像，同时防止发生闪烁和液晶面板的衰减。 要以中间色调显示的数据的显示操作具有在每个帧期间被禁止显示的显示数据的重复帧的一行或多行。 这种被禁止的显示行在连续的帧上以顺序的方式被指定为不同，并且指定序列根据改变的模式在连续的帧中变化。

公开(公告)号：US4404552A

公开(公告)日：1983-09-13

申请号：US220142

申请日：1980-12-23

申请人： Shigeru Hirahata ,  Tetsuya Ikeda ,  Tsuguji Tachiuchi ,  Shigeru Komatsu ,  Teruhiro Takezawa

发明人： Shigeru Hirahata ,  Tetsuya Ikeda ,  Tsuguji Tachiuchi ,  Shigeru Komatsu ,  Teruhiro Takezawa

IPC分类号： G06F17/21 ,  G09G5/36 ,  G09G5/40 ,  G09G1/16

CPC分类号： G09G5/40

摘要： In a display signal generating means in a display device for both the character display and the graphic display, address conversion means is provided for converting the addresses of one character in a plurality of lines of one character section of a memory field corresponding to a display panel into a predetermined address or addresses.

摘要翻译： 在用于字符显示和图形显示的显示装置中的显示信号发生装置中，提供地址转换装置，用于转换对应于显示面板的存储器字段的一个字符部分的多个行中的一个字符的地址 进入预定的地址或地址。

公开(公告)号：US5414571A

公开(公告)日：1995-05-09

申请号：US961623

申请日：1992-10-16

申请人： Hiromi Matsushige ,  Minoru Kosuge ,  Yasuhiro Shimura ,  Hideki Miyasaka ,  Satoshi Minoshima ,  Tsuguji Tachiuchi ,  Kazunori Iwabuchi ,  Terumi Takashi ,  Naoto Matsunami

发明人： Hiromi Matsushige ,  Minoru Kosuge ,  Yasuhiro Shimura ,  Hideki Miyasaka ,  Satoshi Minoshima ,  Tsuguji Tachiuchi ,  Kazunori Iwabuchi ,  Terumi Takashi ,  Naoto Matsunami

IPC分类号： H03H15/00 ,  G11B5/035 ,  G11B20/10 ,  G11B20/18 ,  H03H17/00 ,  H03H21/00 ,  H03K5/159 ,  H04B3/04 ,  H04L25/03 ,  G11B5/35 ,  H03H7/30 ,  H03H7/40

CPC分类号： G11B20/10037 ,  G11B20/10009 ,  G11B20/10046 ,  G11B5/035 ,  H03K5/159 ,  H04L25/03038

摘要： A data reproducing circuit having a magnetic head for reading data from a recording medium, an adaptive equalization circuit for optimizing the waveform of a read signal, a discriminator circuit for discriminating an output signal of the adaptive equalization circuit and outputting a discriminated signal to an upper stage circuit, a format detecting circuit for detecting a pattern of signals written on the recording medium from outputs of the magnetic head, an expected value generating circuit for generating an expected value of the waveform of the read signal in accordance with an output of the adaptive equalization circuit and an output of the discriminator circuit, and an error detecting circuit for generating an error signal representing a difference between an output of the adaptive equalization circuit and an output of the expected value generating circuit. In the data reproducing circuit, the adaptive equalization characteristic of the adaptive equalization circuit is changed when a particular signal pattern on the recording medium is detected, allowing the adaptive equalization operation suitable for the recording medium.

摘要翻译： 一种具有用于从记录介质读取数据的磁头的数据再现电路，用于优化读取信号的波形的自适应均衡电路，用于鉴别自适应均衡电路的输出信号并将鉴别信号输出到上位的鉴频电路 格式检测电路，用于根据磁头的输出来检测写在记录介质上的信号的模式;期望值产生电路，用于根据自适应的输出产生读取信号的波形的期望值 均衡电路和鉴别器电路的输出;以及误差检测电路，用于产生表示自适应均衡电路的输出与预期值产生电路的输出之间的差的误差信号。 在数据再现电路中，当检测到记录介质上的特定信号图案时，自适应均衡电路的自适应均衡特性改变，允许适合于记录介质的自适应均衡操作。

公开(公告)号：US4388621A

公开(公告)日：1983-06-14

申请号：US158263

申请日：1980-06-10

申请人： Shigeru Komatsu ,  Shigeru Hirahata ,  Tsuguji Tachiuchi

发明人： Shigeru Komatsu ,  Shigeru Hirahata ,  Tsuguji Tachiuchi

IPC分类号： G09G5/24 ,  G06F3/153 ,  G09G1/16 ,  G09G5/00 ,  G09G5/397 ,  G09G5/399 ,  G09G1/00

CPC分类号： G09G5/001

摘要： In a .phi..sub.2 cycle steal mode, a clock signal is selected such that a time period during which a RAM is connected to a timing signal generator for display is extended and a time period during which the RAM is connected to a CPU is shortened accordingly, without changing an overall period. This clock signal is used to actuate a switching circuit for the RAM while a clock signal having unmodified duty ratio is applied to the CPU, a ROM and external circuits so that a display data readout period from the RAM is extended without affecting the CPU clock frequency and the operation of other circuits. During this readout period, a plurality of display address signals are applied to the RAM from the timing signal generator and a plurality of data derived from the RAM are sequentially loaded in a register which is then read out at a desired timing to enable the display of a plurality of characters in one CPU clock period.

摘要翻译： 在phi 2循环盗取模式中，选择时钟信号，使得连接到用于显示的定时信号发生器的RAM的时间段被延长，并且相应地缩短RAM连接到CPU的时间段， 而不改变整个时期。 该时钟信号用于激活用于RAM的开关电路，而具有未修改占空比的时钟信号被施加到CPU，ROM和外部电路，使得来自RAM的显示数据读出周期不会影响CPU时钟频率 和其他电路的操作。 在该读出期间，多个显示地址信号从定时信号发生器施加到RAM，并且从RAM导出的多个数据顺序地加载到寄存器中，然后在期望的定时读出寄存器，以使得能够显示 一个CPU时钟周期内的多个字符。

公开(公告)号：US4855728A

公开(公告)日：1989-08-08

申请号：US56128

申请日：1987-06-01

申请人： Hiroyuki Mano ,  Tsuguji Tachiuchi ,  Kiyoshige Kinugawa ,  Shinji Tanaka

发明人： Hiroyuki Mano ,  Tsuguji Tachiuchi ,  Kiyoshige Kinugawa ,  Shinji Tanaka

IPC分类号： G06F3/14 ,  G02F1/133 ,  G06F3/147 ,  G09G3/36 ,  G09G5/00 ,  G09G5/391

CPC分类号： G09G3/3611 ,  G06F3/1475 ,  G09G2310/0221

摘要： A data converting system converts CRT display data into display data for another display unit such as a liquid crystal display unit by use of a memory. The system includes a data load controller which selects one segment of data out of two segments of data in the CRT display data successively while changing the segment position to be selected alternately in every two frame scanning periods so that the CRT display data for one complete picture is written into the memory in two frame scanning periods, i.e., a segment is written into the memory once for every two adjacent segments. Display data is read out of the memory in the data form conformable to the other display unit.

摘要翻译： 数据转换系统通过使用存储器将CRT显示数据转换为诸如液晶显示单元的另一显示单元的显示数据。 该系统包括数据负载控制器，其在CRT显示数据中连续地选择两个数据段中的数据段，同时在每两帧扫描周期中交替地改变要选择的段位置，使得CRT显示数据用于一个完整的图像 在两帧扫描周期中被写入存储器，即，对于每两个相邻的段，将片段写入存储器一次。 以与其他显示单元相符的数据形式从存储器读出显示数据。

公开(公告)号：US4628482A

公开(公告)日：1986-12-09

申请号：US491227

申请日：1983-05-03

申请人： Tsuguji Tachiuchi ,  Toyota Honda

发明人： Tsuguji Tachiuchi ,  Toyota Honda

IPC分类号： G06F7/00 ,  G06F12/00 ,  G06F13/16 ,  G06F13/28 ,  G06F13/42 ,  G11C11/406

CPC分类号： G11C11/406 ,  G06F13/1636 ,  G06F13/287 ,  G06F13/42

摘要： In accordance with the present invention, there is provided a data processing apparatus comprising an MPU which inputs or outputs an address signal and a data signal on the time sharing basis, a latching means for latching said address signal, a memory which must be refreshed, and changeover means for connecting said memory to said MPU during a data signal period and connecting said memory to a refresh counter during remaining periods.

摘要翻译： 根据本发明，提供了一种数据处理装置，包括：MPU，其基于时间共享输入或输出地址信号和数据信号;锁存装置，用于锁存所述地址信号;必须刷新的存储器; 以及切换装置，用于在数据信号周期期间将所述存储器连接到所述MPU，并且在剩余时段期间将所述存储器连接到刷新计数器。