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公开(公告)号：US6092227A
公开(公告)日：2000-07-18
申请号：US18934
申请日：1998-02-05
申请人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
发明人： Hideki Toki , Akira Kitaguchi , Makoto Hatakenaka , Kiyoyuki Shiroshima , Masaaki Matsuo , Tsuyoshi Saitoh
IPC分类号： G01R31/28 , G06F11/22 , G11C11/413 , G11C29/10 , G11C29/34 , G11C29/36 , G11C29/38 , G11C29/56
摘要： A test circuit includes a writing unit that outputs m-bit data captured upon receipt of a clock signal, branches the m-bit data n identical m-bit data signals, and stores the n m-bit data signals in a memory device. A function determining unit reads the n m-bit data signals from the memory, compares one of the n m-bit data signals to an m-bit expected value, and determines coincidence or non-coincidence between the n m-bit data signal and an expected value.
摘要翻译： 测试电路包括写入单元，其输出接收到时钟信号时捕获的m位数据，分配m位数据n个相同的m位数据信号，并将n个m位数据信号存储在存储器件中。 功能确定单元从存储器读取n个m位数据信号，将n个m位数据信号中的一个与m位预期值进行比较，并且确定n个m位数据信号和 一个预期的价值。
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2.发明授权Field effect transistor array including doped two-cell isolation region for preventing latchup 失效场效应晶体管阵列包括用于防止闭锁的掺杂的二单元隔离区
公开(公告)号：US6043522A
公开(公告)日：2000-03-28
申请号：US61090
申请日：1998-04-16
申请人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
发明人： Michio Nakajima , Makoto Hatakenaka , Akira Kitaguchi , Kiyoyuki Shiroshima , Takekazu Yamashita , Masaaki Matsuo
IPC分类号： H01L21/761 , H01L21/8238 , H01L27/092 , H01L27/10 , H01L27/105
CPC分类号： H01L27/105 , H01L21/761 , Y10S257/901 , Y10S257/909
摘要： A semiconductor device capable of solving a problem of a conventional semiconductor device in that a high density integration cannot be expected because each cell, which includes a pair of N and P wells disposed adjacently, requires a countermeasure against latchup individually. The high density integration prevents an effective countermeasure against latchup. The present semiconductor device arranges two cells, which are adjacent in the direction of an alignment of the N wells and P wells, in opposite directions so that two P wells (or two N wells) of the two adjacent cells are disposed successively, and includes an isolation layer extending across the two adjacent cells to enclose the two successively disposed P wells, thereby isolating the two P wells collectively from the substrate.
摘要翻译： 能够解决现有的半导体器件的问题的半导体器件的原因在于，由于包括一对相邻地设置的一对N阱和P阱的每个单元需要单独地闭锁的对策，所以不能期望高密度积分。 高密度集成防止锁定的有效对策。 本半导体装置将N个阱和P个阱的排列方向相邻的两个电池相反地配置，使得两个相邻电池的两个P阱（或两个N阱）相继配置，并且包括 隔离层延伸穿过两个相邻的电池以封闭两个连续设置的P阱，从而将两个P阱与衬底共同隔离。
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3.发明授权Semiconductor memory device and method of refreshing semiconductor memory device 失效半导体存储器件和刷新半导体存储器件的方法
公开(公告)号：US5926429A
公开(公告)日：1999-07-20
申请号：US199050
申请日：1998-11-24
申请人： Tsuyoshi Saitoh , Kiyoyuki Shiroshima , Michio Nakajima , Masaaki Matsuo , Nobuyuki Fujii , Akira Kitaguchi
发明人： Tsuyoshi Saitoh , Kiyoyuki Shiroshima , Michio Nakajima , Masaaki Matsuo , Nobuyuki Fujii , Akira Kitaguchi
IPC分类号： G11C11/406 , G11C7/00
CPC分类号： G11C11/406
摘要： A semiconductor memory device includes memory elements, each maintaining memory contents within a period of time during which a refresh operation is repeated, and a refresh request circuit for making a refresh request. The semiconductor memory device includes refreshing circuits each of which, in response to a refresh request from the refresh request circuit, performs a refresh operation on a different number of memory elements at the same time, and a selecting circuit for selecting one refreshing circuit from among the refreshing circuits according to the number of memory elements included in the semiconductor memory device. The refresh request circuit can change the interval at which it makes a refresh request.
摘要翻译： 半导体存储器件包括存储器元件，每个存储器元件在重复刷新操作的时间段内保持存储器内容，以及刷新请求电路。 半导体存储器件包括刷新电路，每个刷新电路响应于来自刷新请求电路的刷新请求同时对不同数量的存储器元件执行刷新操作，以及选择电路，用于从其中选择一个刷新电路 根据包括在半导体存储器件中的存储元件的数量的刷新电路。 刷新请求电路可以改变刷新请求的间隔。
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4.发明授权Semiconductor device test board and method for evaluating semiconductor devices 失效半导体器件测试板和半导体器件评估方法
公开(公告)号：US6114866A
公开(公告)日：2000-09-05
申请号：US18445
申请日：1998-02-04
申请人： Masaaki Matsuo , Tsuyoshi Saitoh , Takekazu Yamashita , Michio Nakajima , Akira Kitaguchi , Hideki Toki
发明人： Masaaki Matsuo , Tsuyoshi Saitoh , Takekazu Yamashita , Michio Nakajima , Akira Kitaguchi , Hideki Toki
CPC分类号： G01R31/2863 , H01L2924/0002
摘要： A semiconductor device test board solves a problem with conventional test boards in that test results obtained through a burn-in procedure could be identified only before the test board is taken out of a burn-in oven. Hence, conventional test boards required additional steps for checking the test results after removing the test boards from the burn-in oven. This extra step prevents the efficiency of the test from being improved. One embodiment of the present test board has indicator arms, each rotatably mounted on a pivot on the test board, for indicating, in response to a signal on a signal line, the test result of the semiconductor device associated with it. Each of the indicator arms maintains its rest position when no failure has occurred in the semiconductor device associated with it during the test. Each indicator arm changes its position if a failure has occurred in the semiconductor device during the test, and retains one of the two positions until after the test board is taken out of the burn-in oven. Thus, the test result can be determined after taking out the test board from the burn-in oven.
摘要翻译： 半导体器件测试板解决了常规测试板的问题，因为只有在将测试板从老化炉中取出之前，才能识别通过烧录程序获得的测试结果。 因此，常规测试板需要额外的步骤，以便在从老化炉中取出测试板后检查测试结果。 这个额外的步骤可以防止测试的效率得到改善。 本测试板的一个实施例具有指示臂，每个指示臂可旋转地安装在测试板上的枢轴上，用于响应于信号线上的信号，指示与其相关联的半导体器件的测试结果。 当在测试期间与其相关联的半导体器件中没有发生故障时，每个指示器臂保持其静止位置。 如果在测试期间在半导体器件中发生故障，则每个指示臂改变其位置，并且保持两个位置中的一个，直到将测试板从老化炉中取出。 因此，可以在从老化炉中取出测试板之后确定测试结果。
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5.发明授权
公开(公告)号：US6040614A
公开(公告)日：2000-03-21
申请号：US33611
申请日：1998-03-03
申请人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
发明人： Akira Kitaguchi , Makoto Hatakenaka , Michio Nakajima , Kaoru Motonami , Kiyoyuki Shiroshima , Takekazu Yamashita
IPC分类号： H01L27/04 , H01L21/82 , H01L21/822 , H01L21/8242 , H01L23/525 , H01L27/105 , H01L27/108 , H01L29/40
CPC分类号： H01L23/5258 , H01L27/105 , H01L27/108 , H01L2924/0002
摘要： A semiconductor integrated circuit includes a fuse element located on an insulating layer. The surface of the insulating layer is substantially smooth. The insulating layer is located over a capacitor. Wiring is located on the insulation layer. The fuse element and the wiring include the same material.
摘要翻译： 半导体集成电路包括位于绝缘层上的熔丝元件。 绝缘层的表面基本上是光滑的。 绝缘层位于电容器的上方。 接线位于绝缘层上。 熔丝元件和布线包括相同的材料。
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公开(公告)号：US6025733A
公开(公告)日：2000-02-15
申请号：US18055
申请日：1998-02-03
申请人： Tuyoshi Saitoh , Akira Kitaguchi , Masaaki Matsuo , Makoto Hatakenaka , Toshio Nakano , Yuko Sudo
发明人： Tuyoshi Saitoh , Akira Kitaguchi , Masaaki Matsuo , Makoto Hatakenaka , Toshio Nakano , Yuko Sudo
CPC分类号： G11C29/48 , H01L2224/05553 , H01L2224/05554 , H01L2224/0603 , H01L2224/48463
摘要： A semiconductor memory device includes two subcircuits each including a memory circuit, a semiconductor circuit, and a logical circuit. Connection pads are divided into only two parallel rows located along the outer periphery of the semiconductor memory device. Each of the pads may include a probe region against which a probe is pressed for testing the semiconductor memory circuit, and a wire region to which a wire is connected upon packaging.
摘要翻译： 半导体存储器件包括两个子电路，每个子电路包括存储电路，半导体电路和逻辑电路。 连接焊盘被分成仅沿着半导体存储器件的外围设置的两个平行的行。 每个焊盘可以包括：探针被按压的探针区域，用于测试半导体存储器电路;以及导线区域，在包装时连接导线。
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公开(公告)号：US5453993A
公开(公告)日：1995-09-26
申请号：US186107
申请日：1994-01-25
IPC分类号： G01R31/28 , G01R31/30 , H01L21/326 , H01L21/66 , G06F11/00
CPC分类号： G01R31/30
摘要： Disclosed is a semiconductor integrated circuit which can be tested with a high-speed clock of actual operation level or more, even if a relatively low-priced IC tester which is not capable of supplying high-speed clocks is employed, and a method of testing the same. An exclusive OR gate (2) of the semiconductor integrated circuit receives the first test clock (TCLK1) through the first test clock input pin (P1) into the first input and the second test clock (TCLK2) through the second test clock input pin (P2) into the second input, to output a high-speed clock (SCLK) resulting from the test clocks to an A input of a selector (3). Thus, the semiconductor interacted circuit internally generates the high-speed clock having higher frequency than that of the test clock to operate an internal circuit, thereby being tested with clock frequency of actual operation level or more even by means of the relatively low-priced IC tester.
摘要翻译： 公开了一种半导体集成电路，其可以用实际操作电平以上的高速时钟进行测试，即使采用不能提供高速时钟的相对低廉的IC测试器，也可以使用测试方法 一样。 半导体集成电路的异或门（2）通过第一测试时钟输入引脚（P1）将第一测试时钟（TCLK1）通过第二测试时钟输入引脚（P1）接收到第一输入和第二测试时钟（TCLK2） P2）输入到第二输入端，将由测试时钟产生的高速时钟（SCLK）输出到选择器（3）的A输入端。 因此，半导体相互作用的电路在内部生成具有比测试时钟高的频率的高速时钟，以操作内部电路，从而通过相对低价的IC来实际操作电平或更高的时钟频率进行测试 测试仪
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公开(公告)号：US07847714B2
公开(公告)日：2010-12-07
申请号：US12411142
申请日：2009-03-25
IPC分类号： H03M1/20
摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.
摘要翻译： 提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。 ＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。 在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。
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公开(公告)号：US07952506B2
公开(公告)日：2011-05-31
申请号：US12911286
申请日：2010-10-25
IPC分类号： H03M3/00
摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.
摘要翻译： 提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。 ＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。 在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。
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公开(公告)号：US20110037633A1
公开(公告)日：2011-02-17
申请号：US12911286
申请日：2010-10-25
IPC分类号： H03M1/20
摘要： There is provided a technique for reducing the adverse effect of idle tones in the channels in a ΔΣ-type A/D converter including a plurality of channels for converting analog input signals into digital signals. The ΔΣ-type A/D converter includes an L channel for converting a left analog input signal into a digital signal and an R channel for converting a right analog input signal into a digital signal. Each of the L channel and the R channel includes a DC dither circuit for generating a DC addition voltage for shifting the frequency of an idle tone. In the L channel and the R channel, DC addition voltages generated by DC dither circuits are different from each other.
摘要翻译： 提供了一种用于减少包括用于将模拟输入信号转换为数字信号的多个通道的＆Dgr＆amp; S型A / D转换器中的通道中的空闲音调的不利影响的技术。 ＆amp; S＆amp; S型A / D转换器包括用于将左模拟输入信号转换为数字信号的L通道和用于将右模拟输入信号转换为数字信号的R通道。 L沟道和R沟道中的每一个包括用于产生用于移动空闲频率的频率的DC附加电压的DC抖动电路。 在L沟道和R沟道中，由DC抖动电路产生的直流相加电压彼此不同。
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