公开(公告)号：US5614766A

公开(公告)日：1997-03-25

申请号：US556103

申请日：1995-11-09

申请人： Hidemi Takasu ,  Takanori Ozawa ,  Noriyuki Shimoji

发明人： Hidemi Takasu ,  Takanori Ozawa ,  Noriyuki Shimoji

IPC分类号： H01L25/065 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/85 ,  H01L25/0657 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/78301 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06555 ,  H01L24/45 ,  H01L24/78 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082

摘要： The present invention relates to a structure of semiconductor chip joint for mounting a plurality of semiconductor chips onto a single package. The joint comprises two or more semiconductor chips, the chips each having an element formation surface and a rear surface and being piled up with their element formation surfaces directed either in a first direction or in a second direction by turns so that their element formation surfaces are opposed to each other while their rear surfaces are opposed to each other, a bonding pad provided on the element formation surface of the chip directed in the first direction, connecting pad provided on the element formation surface of the chip directed both in the first direction and in the second direction;wherein the chip whose element formation surface is directed in the second direction is piled on so that the bonding pad of the chip whose element formation surface is directed in the first direction is exposed, and the chip whose element formation surface is directed in the first direction and the chip whose element formation surface is directed in the second direction are electrically connected to each other through their respective connecting pads with a conductive bump.

摘要翻译： 本发明涉及用于将多个半导体芯片安装到单个封装上的半导体芯片接头的结构。 接头包括两个或更多个半导体芯片，每个芯片均具有元件形成表面和后表面，并且它们的元件形成表面被堆积在其第一方向或第二方向上，以使它们的元件形成表面是 在其后表面彼此相对的情况下彼此相对;焊盘，设置在沿着第一方向指向的芯片的元件形成表面上;连接焊盘，设置在芯片的元件形成表面上，两者沿第一方向指向;以及 在第二个方向 其中将元件形成表面朝向第二方向的芯片堆叠在一起，使得元件形成表面沿第一方向指向的芯片的焊盘露出，并且其元件形成表面沿第一方向 并且其元件形成表面在第二方向上引导的芯片通过其各自的连接焊盘彼此电连接，并具有导电凸块。

公开(公告)号：US5402374A

公开(公告)日：1995-03-28

申请号：US235326

申请日：1994-04-29

申请人： Masataka Tsuruta ,  Noriyuki Shimoji ,  Hironobu Nakao ,  Takanori Ozawa

发明人： Masataka Tsuruta ,  Noriyuki Shimoji ,  Hironobu Nakao ,  Takanori Ozawa

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/16 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L29/66825 ,  G11C16/16 ,  H01L21/2815 ,  H01L29/4232 ,  H01L29/7883

摘要： In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film and the floating gate are formed spaced apart from the source region by a predetermined offset distance. A sidewall gate which is insulated from the channel region and the floating gate is provided in an offset distance portion on the channel region. An offset region immediately under the sidewall gate functions as an inversion layer, thereby to make it possible to read out information at high speed utilizing the inversion of the offset region.

摘要翻译： 在根据本发明的非易失性半导体存储器件中，浮置栅极通过隧道绝缘膜设置在介于源极区和漏极区之间的沟道区上。 隧道绝缘膜和浮栅形成与源极区间隔开预定的偏移距离。 与通道区域和浮动栅极绝缘的侧壁栅极设置在沟道区域上的偏移距离部分中。 侧壁栅极正下方的偏移区域用作反转层，从而可以利用偏移区域的反转来高速读出信息。

公开(公告)号：US5332915A

公开(公告)日：1994-07-26

申请号：US964043

申请日：1992-10-21

申请人： Noriyuki Shimoji ,  Takanori Ozawa ,  Hironobu Nakao

发明人： Noriyuki Shimoji ,  Takanori Ozawa ,  Hironobu Nakao

IPC分类号： G11C17/00 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/517 ,  H01L29/792

摘要： A high dielectric film instead of an oxidizing film conventionally used is used in the non-volatile memory of an MoNoS construction. Using a mixed film composed of a high dielectric constant film and an amorphous insulating film for the trap film, the ratio of the voltage applied to the tunnel oxidizing film is increased so that writing and erasing operations can be effected with a low voltage. Penetration of the electrons into the electrode and the flow of positive holes from the electrode are prevented so as to increase the flow efficiency.

摘要翻译： 在MoNoS结构的非易失性存储器中使用代替常规使用的氧化膜的高介电膜。 使用由高介电常数膜和非晶绝缘膜组成的混合膜用于陷阱膜，施加到隧道氧化膜的电压的比率增加，从而可以以低电压进行写入和擦除操作。 防止电子进入电极的渗透和来自电极的空穴的流动，从而提高流动效率。

公开(公告)号：US5319229A

公开(公告)日：1994-06-07

申请号：US874497

申请日：1992-04-27

申请人： Noriyuki Shimoji ,  Takanori Ozawa ,  Hironobu Nakao

发明人： Noriyuki Shimoji ,  Takanori Ozawa ,  Hironobu Nakao

IPC分类号： H01L21/8247 ,  G11C16/04 ,  H01L21/28 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/34 ,  H01L29/68 ,  H01L29/78

CPC分类号： H01L21/28202 ,  G11C16/0466 ,  H01L29/513 ,  H01L29/518 ,  H01L29/792

摘要： A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.

摘要翻译： 半导体非易失性存储器。 存储单元具有以下结构。 在P型硅衬底3中，设置有n +型源极26和n +型漏极28，两个区域形成沟道区30。在沟道区域30的顶部层叠有二氧化硅膜5，绝缘 由氮化物膜18a，18b和18c以及氧化物膜20a，20b和20c组成的层。 此外，在绝缘层的顶部，形成用作控制电极的多晶硅膜24。 通过使用存储单元和行选择晶体管，可以构成半导体非易失性存储器。

公开(公告)号：US5286994A

公开(公告)日：1994-02-15

申请号：US902896

申请日：1992-06-23

申请人： Takanori Ozawa ,  Noriyuki Shimoji

发明人： Takanori Ozawa ,  Noriyuki Shimoji

IPC分类号： G11C17/00 ,  H01L21/28 ,  H01L21/8247 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  H01L29/34 ,  H01L29/78

CPC分类号： H01L29/513 ,  H01L29/518 ,  H01L29/792 ,  H01L21/28202

摘要： A trap film assembly of a semiconductor memory device includes a tunnel oxide layer formed on a semiconductor substrate and plural multi-layer film layers laminated on the tunnel oxide film. A thickness of each multi-layer film layer is sequentially increased in a direction away from the semiconductor substrate and towards a gate electrode, thereby displacing the charge centroid of the assembly towards the semiconductor substrate.

摘要翻译： 半导体存储器件的陷阱膜组件包括形成在半导体衬底上的隧道氧化物层和层叠在隧道氧化物膜上的多个多层膜层。 每个多层膜层的厚度在远离半导体衬底并朝向栅电极的方向上依次增加，从而将组件的电荷重心移向半导体衬底。

公开(公告)号：US09003614B2

公开(公告)日：2015-04-14

申请号：US13638941

申请日：2010-04-02

申请人： Takanori Ozawa ,  Keiichi Keyaki ,  Ryuta Kumano

发明人： Takanori Ozawa ,  Keiichi Keyaki ,  Ryuta Kumano

IPC分类号： A44B19/30 ,  A44B19/26

CPC分类号： A44B19/26 ,  Y10T24/2586 ,  Y10T24/2588

摘要： Engaged portions formed on a tab holder are elastically engaged and attached to engaging portions formed on a first column portion and the rear side of a second column portion on an upper blade, and a pair of protrusions formed on the inner side of the tab holder are fitted in a recession formed on an inclined surface of the first column portion and a recession formed on an inclined surface of the second column portion. Further, stepped portions formed at both edge portions of both front and rear ends of the tab holder are brought in contact with end surfaces and inner sides of support walls installed at both edge portions of inclined surfaces. The slide fastener can improve attachment strength of the tab holder, implement excellent durability for a long period of time, excellent external appearance, and excellent assembly performance.

摘要翻译： 形成在翼片保持器上的啮合部分弹性地接合并附接到形成在上刀片上的第一柱部分和第二柱部分的后侧上的接合部分，并且形成在拉片保持器的内侧上的一对突起是 安装在形成在第一柱部分的倾斜表面上的凹陷中，以及形成在第二柱部分的倾斜表面上的凹陷。 此外，形成在突片保持器的前端和后端的两个边缘部分处的阶梯部分与安装在倾斜表面的两个边缘部分处的支撑壁的端面和内侧接触。 该拉链可以提高拉片支架的附着强度，长期实现优异的耐久性，优异的外观和优异的组装性能。

公开(公告)号：US6094369A

公开(公告)日：2000-07-25

申请号：US100263

申请日：1998-06-19

申请人： Takanori Ozawa ,  Takaaki Fuchikami

发明人： Takanori Ozawa ,  Takaaki Fuchikami

IPC分类号： H01L21/8247 ,  G11C11/22 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C11/22

摘要： A nonvolatile memory element capable of using desired ferroelectric materials, exhibiting a high reliability and performing processings such as reading of information without destruction of stored contents is provided. A memory cell comprises two capacitors Cf1 and Cf2 connected to each other in series. Both capacitors are ferroelectric capacitors manufactured by the same steps. Accordingly, the coupling ratio between both capacitors can be changed by only the change of surface areas thereof. A voltage corresponding to the information to be stored is applied to the opposite ends of the memory cell 20 to cause polarization reversal and as a result, the information is written thereinto. In order to read the stored information, a ground potential is applied to the opposite ends of the memory cell 20. On the basis of the potential generated at a connection 20c upon the application of the ground potential, the information can be read.

摘要翻译： 提供能够使用期望的铁电材料的非易失性存储元件，其具有高可靠性并且执行诸如读取信息而不破坏存储的内容的处理。 存储单元包括彼此串联连接的两个电容器Cf1和Cf2。 两个电容器都是通过相同步骤制造的铁电电容器。 因此，两电容器之间的耦合比只能通过其表面积的变化来改变。 对应于要存储的信息的电压被施加到存储单元20的相对端，以引起极化反转，结果写入信息。 为了读取所存储的信息，将地电位施加到存储单元20的相对端。基于在施加地电位时在连接20c处产生的电位，可以读取信息。

公开(公告)号：US5477068A

公开(公告)日：1995-12-19

申请号：US32119

申请日：1993-03-17

申请人： Takanori Ozawa

发明人： Takanori Ozawa

IPC分类号： G11C16/04 ,  H01L29/423 ,  H01L29/788

CPC分类号： G11C16/0433 ,  H01L29/42328 ,  H01L29/7885

摘要： A pair of impurity regions are formed at a specified interval in a semiconductor substrate. A channel region is defined between the impurity regions. A select gate is provided on the channel region, and a sidewall for holding electric charge is provided along a side of the select gate. A tunnel insulating film is interposed between the sidewall for holding electric charge and the channel region. An insulating film covers the sidewall for holding electric charge. A control gate is provided on the insulating film lying over the sidewall. In such a structure, since the select gate can have a large cross-sectional area, speed-up of the reading can be attained.

摘要翻译： 在半导体衬底中以指定的间隔形成一对杂质区。 在杂质区域之间限定沟道区域。 在通道区域设置选择栅极，沿着选择栅极侧设置用于保持电荷的侧壁。 隧道绝缘膜介于用于保持电荷的侧壁和沟道区之间。 绝缘膜覆盖侧壁以保持电荷。 在位于侧壁上的绝缘膜上设置控制栅极。 在这种结构中，由于选择栅极可以具有大的横截面积，所以可以实现读取的加速。

公开(公告)号：US08806725B2

公开(公告)日：2014-08-19

申请号：US13387749

申请日：2009-07-29

申请人： Keiichi Keyaki ,  Takanori Ozawa

发明人： Keiichi Keyaki ,  Takanori Ozawa

IPC分类号： A44B19/38 ,  A44B19/26

CPC分类号： A44B19/382 ,  Y10T24/2509 ,  Y10T24/2582 ,  Y10T24/2593

摘要： A slide fastener according to the invention includes a left-and-right pair of first and second fastener stringers, a box pin provided on the first fastener stringer, an insert pin provided on the second fastener stringer, and a pair of first and second sliders. The box pin has a box pin body, a stopper portion, and a ridge portion formed on the box pin body. Further, a chamfered portion is formed on an inner surface of at least one of the upper and lower wing plates of the first slider. The ridge portion is arranged at a position in close contact with the chamfered portion of the first slider when the first slider is stopped at the stopper portion. With this arrangement, it becomes possible to cause the user to be accustomed to securely slide the first slider to the normal insert-pin inserting position.

摘要翻译： 根据本发明的拉链包括左右一对第一和第二紧固件桁条，设置在第一拉链条上的盒销，设置在第二拉链条上的插销，以及一对第一和第二滑动件 。 盒销具有盒销主体，止动部分和形成在盒销主体上的脊部。 此外，在第一滑动件的上翼板和下翼板中的至少一个的内表面上形成有倒角部。 当第一滑块停止在止动部分时，脊部布置在与第一滑块的倒角部紧密接触的位置。 通过这种布置，可以使用户习惯于将第一滑块稳固地滑动到正常的插入销插入位置。

公开(公告)号：US08661628B2

公开(公告)日：2014-03-04

申请号：US13387765

申请日：2009-07-30

申请人： Keiichi Keyaki ,  Takanori Ozawa

发明人： Keiichi Keyaki ,  Takanori Ozawa

IPC分类号： A44B19/38

CPC分类号： A44B19/382 ,  A44B19/388

摘要： A slide fastener includes a pair of first and second fastener stringers, a box pin, an insert pin, and a pair of first and second sliders. The box pin has a box pin body, a stopper portion arranged at a front end side of the box pin body, and suppressing portions projected on at least one of upper and lower surfaces of the box pin body to suppress sliding of the second slider. Further, the box pin body has a body region, and a notched region arranged at an element-row-side base end portion and having excluded a side surface portion at a side facing the insert pin. The suppressing portions are projected in only the notched region. With this arrangement, the second slider can be stably held at an insert-pin inserting position, and a subsequent insert operation or extract operation of the insert pin can be smoothly performed.

摘要翻译： 拉链包括一对第一和第二紧固件桁条，盒销，插入销和一对第一和第二滑块。 盒销具有盒销主体，布置在盒销主体的前端侧的止挡部分和突出在盒销主体的上表面和下表面中的至少一个上的抑制部分，以抑制第二滑块的滑动。 此外，盒子针体具有主体区域和布置在元件行侧基端部处的缺口区域，并且在面向插入销的一侧排除了侧面部分。 抑制部仅在缺口区域突出。 通过这种结构，可以将第二滑块稳定地保持在插入销插入位置，并且可以平稳地执行插入销的随后的插入操作或提取操作。