摘要:
In the non-volatile semiconductor memory device according to the present invention, a floating gate is provided on a channel region which is interposed between a source region and a drain region through a tunnel insulation film. The tunnel insulation film and the floating gate are formed spaced apart from the source region by a predetermined offset distance. A sidewall gate which is insulated from the channel region and the floating gate is provided in an offset distance portion on the channel region. An offset region immediately under the sidewall gate functions as an inversion layer, thereby to make it possible to read out information at high speed utilizing the inversion of the offset region.
摘要:
A trap film assembly of a semiconductor memory device includes a tunnel oxide layer formed on a semiconductor substrate and plural multi-layer film layers laminated on the tunnel oxide film. A thickness of each multi-layer film layer is sequentially increased in a direction away from the semiconductor substrate and towards a gate electrode, thereby displacing the charge centroid of the assembly towards the semiconductor substrate.
摘要:
The present invention relates to a structure of semiconductor chip joint for mounting a plurality of semiconductor chips onto a single package. The joint comprises two or more semiconductor chips, the chips each having an element formation surface and a rear surface and being piled up with their element formation surfaces directed either in a first direction or in a second direction by turns so that their element formation surfaces are opposed to each other while their rear surfaces are opposed to each other, a bonding pad provided on the element formation surface of the chip directed in the first direction, connecting pad provided on the element formation surface of the chip directed both in the first direction and in the second direction;wherein the chip whose element formation surface is directed in the second direction is piled on so that the bonding pad of the chip whose element formation surface is directed in the first direction is exposed, and the chip whose element formation surface is directed in the first direction and the chip whose element formation surface is directed in the second direction are electrically connected to each other through their respective connecting pads with a conductive bump.
摘要:
A high dielectric film instead of an oxidizing film conventionally used is used in the non-volatile memory of an MoNoS construction. Using a mixed film composed of a high dielectric constant film and an amorphous insulating film for the trap film, the ratio of the voltage applied to the tunnel oxidizing film is increased so that writing and erasing operations can be effected with a low voltage. Penetration of the electrons into the electrode and the flow of positive holes from the electrode are prevented so as to increase the flow efficiency.
摘要:
A semiconductor Nonvolatile memory. The memory cell has the following structure. Within a P type silicon substrate 3, there are provided an n.sup.+ type source 26 and an n.sup.+ type drain 28, the two regions forming a channel region 30. On top of the channel region 30 there are laminated a silicon dioxide film 5, an insulating layer which consists of the nitride film 18a,18b and 18c, and the oxide film 20a,20b and 20c. Further, on top of the insulating layer, there is formed a polysilicon film 24, which serves as a control electrode. By using the memory cell and row select transistor a semiconductor nonvolatile memory can be constructed.
摘要:
An organic luminescent device according to the present invention includes a substrate, an organic luminescent layer, and a reflection electrode. Here, the substrate has first and second principal surfaces opposed to each other; the organic luminescent layer is arranged on the first principal surface of the substrate, and is held between a pair of electrodes at least one of which is a transparent electrode; and the reflection electrode is adjacent to a luminescent area of the organic luminescent layer and is arranged on a front surface or a back surface of the transparent electrode. The transparent electrode is arranged on the first principal surface of the substrate, while the reflection electrode is arranged on the transparent electrode. The second principal surface of the substrate is formed into a rough surface at least on its part opposed to the reflection electrode. This configuration improves light extraction efficiency.
摘要:
A method of producing a semiconductor device is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.
摘要:
An independent active region K42 is composed by consecutively providing the source region S42 and S53 of the memory cell MC42 and MC53 between the word line WL2, WL3. The memory cell MC42 and MC53 are connected to the word line WL2, WL3 respectively. Another independent active region K53 is composed by consecutively providing the drain region D53 and D64 of the memory cell MC53 and MC64 between the word line WL3, WL4. The bit line BL3 is formed by connecting each of the independent active regions K30, K31, K32 and K33 with polysilicon respectively. Each of the independent active regions include each of the drain regions D41, D42, D43 and D44 of the memory cells MC41, MC42, MC43 and MC44. Also, the bit line BL4 is formed by connecting each of the independent active regions K41, K42, K43 and K44 with polysilicon respectively. Each of the independent active regions comprises the source regions S41, S42, S43 and S44 respectively.
摘要:
A semiconductor device having a high-speed device and a uniform plane bearing is provided. Device formation regions (51, 52, and 55) are formed on upper surfaces of the silicon substrate (21 and 22), and device isolation regions (9) acting as insulating layer are formed therebetween. The silicon substrate is etched to shape a bottom recessed part (8). The bottom recessed part (8) is formed in such a manner that it borders on the device isolation region (9) and allows the device formation regions (51, 52, and 55) to be emerged therefrom. This structure enables a pn junction to be eliminated, realizing a semiconductor device capable of high-speed operation. Further, each device is formed in an N.sup.- type silicon layer (22) which is grown from the silicon substrate, and thereafter is insulated by forming the bottom recessed part (8). Accordingly, the semiconductor device has a uniform plane bearing.
摘要:
The present invention can provide the memory circuit which has advantages in integration and the manufacturing expense and is easy to manufacture. The nonvolatile memory 21 comprises a P type well for which a N+ type source 4 and a N+ type drain 3 are provided. A surface of a space between the source 4 and the drain 3 comprises a first portion 10a and a second portion 10b. An insulating layer 6 for holding electrons spans the surface of the space. A memory gate electrode 5 is on the insulating layer 6 and spans the first portion 10a. A body 23 of high dielectric material is formed on the surface of the insulating layer 6 so that it connects to the memory gate electrode 5 through an insulating film 8 and spans the second portion 10b.