公开(公告)号：US5543347A

公开(公告)日：1996-08-06

申请号：US363941

申请日：1994-12-27

申请人： Hideo Kawano ,  Keiji Shiotani ,  Masao Mikami ,  Tatsuya Suzuki ,  Seiichi Shishiguchi

发明人： Hideo Kawano ,  Keiji Shiotani ,  Masao Mikami ,  Tatsuya Suzuki ,  Seiichi Shishiguchi

IPC分类号： H01L21/302 ,  H01L21/02 ,  H01L21/20 ,  H01L21/3065 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L28/84 ,  Y10S148/138 ,  Y10S438/964

摘要： First, a metal layer is deposited on a silicon film surface to form a silicide layer in an interface between the silicon film and the metal layer. Subsequently, the metal layer is all removed by etching such that silicide islands are left on the surface of the silicon film, and then the exposed silicon film surface is dry-etched by using the silicide islands as a selective mask.

摘要翻译： 首先，在硅膜表面上沉积金属层，以在硅膜和金属层之间的界面中形成硅化物层。 随后，通过蚀刻去除金属层，使得硅膜的表面上留下硅化物岛，然后通过使用硅化物岛作为选择性掩模来干蚀刻暴露的硅膜表面。

公开(公告)号：US5858853A

公开(公告)日：1999-01-12

申请号：US550624

申请日：1995-10-31

申请人： Seiichi Shishiguchi ,  Tatsuya Suzuki ,  Hideo Kawano ,  Keiji Shiotani ,  Masao Mikami

发明人： Seiichi Shishiguchi ,  Tatsuya Suzuki ,  Hideo Kawano ,  Keiji Shiotani ,  Masao Mikami

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/31 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L28/84 ,  H01L29/94 ,  Y10S148/014

摘要： In a method for forming a capacitor, after preparing a substrate having at least one device area thereon, an amorphous silicon film containing one type of dopant is formed on the device area. A mask layer comprising mask islands is formed and distributed on a surface of the amorphous silicon film. The surface of the amorphous silicon is dry-etched by using the mask layer as a selective etching mask to produce a jagged surface having a lot of protrusions. After forming the jagged surface, the amorphous silicon film is changed into a polycrystalline silicon film serving as a storage electrode. Finally, a dielectric film and then another storage electrode are formed sequentially on the jagged surface of the storage electrode.

摘要翻译： 在形成电容器的方法中，在制备其上具有至少一个器件面积的衬底之后，在器件区域上形成含有一种类型的掺杂剂的非晶硅膜。 包含掩模岛的掩模层形成并分布在非晶硅膜的表面上。 通过使用掩模层作为选择性蚀刻掩模对非晶硅的表面进行干蚀刻，以产生具有大量突起的锯齿状表面。 在形成锯齿状表面之后，将非晶硅膜变成用作存储电极的多晶硅膜。 最后，在存储电极的锯齿状表面上依次形成电介质膜，然后形成另一个存储电极。

公开(公告)号：US4992301A

公开(公告)日：1991-02-12

申请号：US247850

申请日：1988-09-22

申请人： Seiichi Shishiguchi ,  Fumitoshi Toyokawa ,  Masao Mikami

发明人： Seiichi Shishiguchi ,  Fumitoshi Toyokawa ,  Masao Mikami

IPC分类号： C30B25/12 ,  C30B25/14

CPC分类号： C30B25/12 ,  C30B25/14 ,  Y10S148/006 ,  Y10S438/935

摘要： A chemical vapor deposition apparatus includes a reaction tube, a substrate-holder installed in the reaction tube, the substrate-holder holding a plurality of substrates in a vertical direction, surfaces of the substrates being held horizontally, a rotating-means for rotating the substrate-holder, a heating-means for heating the substrates, a first gas-supply nozzle tube installed vertically in the reaction tube, the first gas-supply nozzle tube having a first vertical gas-emission line of a plurality of first gas-emission holes aligned in a vertical direction, and a second gas-supply nozzle tube installed vertically in the reaction tube, the second gas-supply nozzle tube having a second vertical gas-emission line, a plurality of second gas-emission holes aligned in a vertical direction, a first gas-emitting-axis of the first gas-emission holes intersecting with a second gas-emitting-axis of the second gas-emission holes at a first intersection over the substrate, the first intersection of the first and second gas-emitting axes being deviated from the rotation center of the substrate-holder.

公开(公告)号：US5951774A

公开(公告)日：1999-09-14

申请号：US967058

申请日：1997-11-10

申请人： Seiichi Shishiguchi ,  Tohru Aoyama ,  Tatsuya Suzuki

发明人： Seiichi Shishiguchi ,  Tohru Aoyama ,  Tatsuya Suzuki

IPC分类号： C30B25/02 ,  C23C16/44 ,  C23C16/458 ,  C23C16/46 ,  C30B25/12 ,  H01L21/20 ,  H01L21/205 ,  C23C16/00

CPC分类号： C23C16/4581 ,  C23C16/46

摘要： A vapor-phase growth system able to avoid fluctuation of the heating performance of a heater during repeated growth processes is provided. This system includes a reactor, a substrate holder for holding a substrate, and a heater for heating the substrate held by the holder. The holder and the heater are placed in an inner space of the reactor. The holder and the substrate held by the holder divide an inner space of the reactor to thereby form a growth chamber in which a thin film is grown during a growth process and a heater chamber in which the heater is placed. The holder has a supporting member on which the substrate is placed. At least a part of the member is made of the same material as that of the thin film. The supporting member is made of a SOI substrate.

摘要翻译： 提供了能够避免反复生长过程中加热器加热性能波动的气相生长系统。 该系统包括反应器，用于保持基板的基板保持器和用于加热由保持器保持的基板的加热器。 保持器和加热器被放置在反应器的内部空间中。 保持器和由保持器保持的基板分隔反应器的内部空间，从而形成生长室，其中在生长过程中生长薄膜和其中放置加热器的加热器室。 保持器具有支撑构件，衬底放置在支撑构件上。 构件的至少一部分由与薄膜相同的材料制成。 支撑构件由SOI衬底制成。

公开(公告)号：US06258635B1

公开(公告)日：2001-07-10

申请号：US09164970

申请日：1998-10-01

申请人： Kousuke Miyoshi ,  Seiichi Shishiguchi

发明人： Kousuke Miyoshi ,  Seiichi Shishiguchi

IPC分类号： H01L21335

CPC分类号： H01L21/28211 ,  H01L21/26513 ,  H01L21/28167 ,  H01L21/3221

摘要： A method of manufacturing a semiconductor device has a step whereby, when forming a gate oxide film, a thin oxide film is left on a silicon substrate onto which it is formed and whereby a heavy metal at the surface of the silicon substrate is diffused into the substrate, and a step of forming a gate oxide film onto the silicon substrate.

摘要翻译： 一种制造半导体器件的方法具有以下步骤：当形成栅极氧化膜时，在其所形成的硅衬底上留下薄的氧化膜，由此将硅衬底表面的重金属扩散到 衬底，以及在硅衬底上形成栅极氧化膜的步骤。

公开(公告)号：US5894037A

公开(公告)日：1999-04-13

申请号：US749649

申请日：1996-11-15

申请人： Hiroaki Kikuchi ,  Seiichi Shishiguchi

发明人： Hiroaki Kikuchi ,  Seiichi Shishiguchi

IPC分类号： H01L21/322 ,  B05D3/02

CPC分类号： H01L21/3221 ,  Y10S148/06 ,  Y10S148/147 ,  Y10T428/31663

摘要： A silicon semiconductor substrate including a silicon semiconductor layer at one of upper and lower surfaces thereof, the silicon semiconductor layer being composed of polysilicon or noncrystal silicon and containing oxygen in the range of 2 atomic % to 20 atomic % both inclusive, nitrogen in the range of 4 atomic % to 20 atomic % both inclusive, or both nitrogen at 2 atomic % or greater and oxygen at 1 atomic % or greater. The polysilicon or noncrystal silicon semiconductor layer acts as a core for extrinsic gettering. In the silicon semiconductor substrate, the gettering performance is not deteriorated, even if the silicon semiconductor substrate experiences thermal treatment. Thus, it is possible to get rid of contamination caused by heavy metals in the silicon semiconductor substrate.

摘要翻译： 一种硅半导体衬底，包括在其上表面和下表面中的一个上的硅半导体层，所述硅半导体层由多晶硅或非晶硅构成，并且包含在2原子％至20原子％范围内的氧，范围内的氮 为4原子％以上且20原子％以下的氮，2原子％以上的氮和1原子％以上的氧。 多晶硅或非晶硅半导体层作为外部吸气的核心。 在硅半导体基板中，即使硅半导体基板经受热处理，吸气性能也不会劣化。 因此，能够消除硅半导体基板中的重金属引起的污染。

公开(公告)号：US6010914A

公开(公告)日：2000-01-04

申请号：US958666

申请日：1997-10-28

申请人： Seiichi Shishiguchi

发明人： Seiichi Shishiguchi

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L21/66 ,  H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L22/12

摘要： A method for manufacturing a semiconductor device comprises the steps of forming consecutively a silicon oxide layer and a test epitaxial layer in a test pattern area on a silicon wafer, forming an epitaxial layer in a product area for semiconductor devices and on the test epitaxial layer simultaneously, measuring a total thickness of the epitaxial layer and the test epitaxial layer formed in the test pattern area by infrared interference, and determining the thickness of the epitaxial layer formed in the product area based on the total thickness to control the thickness of the epitaxial layer in the product area. A thickness control for a very thin epitaxial layer can be obtained.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在硅晶片的测试图形区域中连续地形成氧化硅层和测试外延层，在半导体器件的产品区域和测试外延层上同时形成外延层 通过红外干涉测量在测试图形区域中形成的外延层和测试外延层的总厚度，并且基于总厚度确定在产品区域中形成的外延层的厚度以控制外延层的厚度 在产品领域。 可以获得非常薄的外延层的厚度控制。

公开(公告)号：US5821158A

公开(公告)日：1998-10-13

申请号：US703735

申请日：1996-08-27

申请人： Seiichi Shishiguchi

发明人： Seiichi Shishiguchi

IPC分类号： C30B23/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/265 ,  H01L21/302 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/336

CPC分类号： H01L29/66628 ,  H01L21/02063 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/30604 ,  Y10S438/974

摘要： On treating a substrate surface of a single crystal silicon substrate, Ge ions are preliminarily implanted into the substrate surface to be formed as a Ge-implanted silicon film on the single crystal silicon substrate. A film surface of Ge-implanted silicon film is treated by oxidizing the film surface to form a spontaneous oxide film. Subsequently, the spontaneous oxide film is subjected to a heat treatment in a reduced-pressure atmosphere to remove the spontaneous oxide film. Alternatively, the spontaneous oxide film is subjected to a heat treatment with a reducing gas of, for example, a hydrogen gas, a silane-based gas, or a GeH.sub.4 gas supplied onto the spontaneous oxide film to remove the spontaneous oxide film. Preferably, the Ge ions are preliminarily implanted into the substrate surface to be formed as Ge-implanted silicon film which consists, in atomic percent, essentially of at least 1% Ge.

摘要翻译： 在处理单晶硅衬底的衬底表面时，预先将Ge离子注入到在单晶硅衬底上作为Ge注入硅膜形成的衬底表面。 通过氧化膜表面来处理Ge注入硅膜的膜表面以形成自发氧化膜。 随后，在减压气氛中对自发氧化膜进行热处理以除去自发氧化膜。 或者，通过供给到自发氧化膜上的例如氢气，硅烷系气体，GeH 4气体的还原气体对自发氧化膜进行热处理，除去自发氧化膜。 优选地，将Ge离子预先注入到待形成的Ge衬底硅膜的衬底表面中，其中原子百分比基本上由至少1％Ge组成。

公开(公告)号：US5798544A

公开(公告)日：1998-08-25

申请号：US242345

申请日：1994-05-13

申请人： Shuichi Ohya ,  Masato Sakao ,  Yoshihiro Takaishi ,  Kiyonori Kajiyana ,  Takeshi Akimoto ,  Shizuo Oguro ,  Seiichi Shishiguchi

发明人： Shuichi Ohya ,  Masato Sakao ,  Yoshihiro Takaishi ,  Kiyonori Kajiyana ,  Takeshi Akimoto ,  Shizuo Oguro ,  Seiichi Shishiguchi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10823 ,  H01L27/10808

摘要： Disclosed herein is a semiconductor memory device including a plurality of memory cells each includes an active region which is defined in a column direction by a pair of trench isolation regions formed in a semiconductor substrate and in a row direction by an isolation gate conductor lines formed on a first gate insulating film covering the substrate, a source and a drain region selectively formed in the active region to define a channel region of a cell transistor, a second gate insulating film formed on the channel region, a word line formed on the second gate insulating film, a first insulating film covering the active region and the word line, a bit line formed on the first insulating film to overlap with the isolation gate conductor, a bit line connection conductor formed in the first insulating film to connect the drain region to the bit line with being in contact with the sidewall surface of the bit line, a second insulating film covering the bit line and the first insulating film, and a storage capacitor having a capacitor electrode connected to the source region through a contact hole provided in the first and second insulating film.

摘要翻译： 这里公开了一种半导体存储器件，其包括多个存储单元，每个存储单元包括有源区，该有源区通过在半导体衬底中形成的一对沟槽隔离区而在列方向上限定，并且在行方向上由隔离栅导体线形成 覆盖基板的第一栅极绝缘膜，选择性地形成在有源区中的源极和漏极区域，以限定单元晶体管的沟道区，形成在沟道区上的第二栅极绝缘膜，形成在第二栅极上的字线 绝缘膜，覆盖有源区和字线的第一绝缘膜，形成在第一绝缘膜上以与隔离栅导体重叠的位线;形成在第一绝缘膜中的位线连接导体，以将漏区连接到 位线与位线的侧壁表面接触，覆盖位线的第二绝缘膜和第一绝缘f 以及具有通过设置在第一和第二绝缘膜中的接触孔连接到源极区的电容器电极的存储电容器。

公开(公告)号：US06190976B1

公开(公告)日：2001-02-20

申请号：US09198763

申请日：1998-11-24

申请人： Seiichi Shishiguchi ,  Tomoko Yasunaga

发明人： Seiichi Shishiguchi ,  Tomoko Yasunaga

IPC分类号： H01L21336

CPC分类号： H01L29/665 ,  H01L29/41783 ,  H01L29/456 ,  H01L29/4941

摘要： A fabrication method of a semiconductor device with an IGFET is provided, which makes it possible to decrease the current leakage due to electrical short-circuit between a gate electrode and source/drain regions of the IGFET through conductive grains deposited on its dielectric sidewalls. After the basic structure of the IGFET is formed, first and second single-crystal Si epitaxial layers are respectively formed on the first and second source/drain regions by a selective epitaxial growth process. Then, the surface areas of the first and second single-crystal Si epitaxial layers are oxidized, and the oxidized surface areas of the first and second single-crystal Si epitaxial layers are removed by etching. If unwanted grains of poly-Si or amorphous Si are grown on the first and second dielectric sidewalls in the selective epitaxial growth process, the unwanted grains are oxidized and removed, thereby preventing electrical short-circuit from occurring between the gate electrode and the first and second source/drain regions through the unwanted grains deposited on the first and second dielectric sidewalls.

摘要翻译： 提供了具有IGFET的半导体器件的制造方法，这使得可以通过沉积在其电介质侧壁上的导电晶粒来减小由IGFET的栅极电极和源极/漏极区域之间的电短路引起的电流泄漏。 在形成IGFET的基本结构之后，通过选择性外延生长工艺在第一和第二源/漏区上分别形成第一和第二单晶Si外延层。 然后，第一和第二单晶Si外延层的表面积被氧化，并且通过蚀刻去除第一和第二单晶Si外延层的氧化表面积。 如果在选择性外延生长工艺中在多晶硅或非晶Si的不想要的晶粒生长在第一和第二电介质侧壁上，则不需要的晶粒被氧化和去除，从而防止在栅电极和第一和第二电介质侧壁之间发生电短路 通过沉积在第一和第二电介质侧壁上的不需要的晶粒的第二源/漏区。