利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

368 条记录 (耗时 0.025 秒)

    Semiconductor memory device with address transition detection and timing control
    3.
    发明授权
    Semiconductor memory device with address transition detection and timing control 失效
    具有地址转换检测和定时控制的半导体存储器件

    公开(公告)号：US4843596A

    公开(公告)日：1989-06-27

    申请号：US124554

    申请日：1987-11-24

    申请人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

    发明人： Hideshi Miyatake ,  Masaki Kumanoya ,  Hideto Hidaka ,  Yasuhiro Konishi ,  Katsumi Dosaka ,  Hiroyuki Yamasaki ,  Masaki Shimoda ,  Yuto Ikeda ,  Kazuhiro Tsukamoto

    IPC分类号： G11C11/401 ,  G11C7/22 ,  G11C8/18

    CPC分类号： G11C8/18 ,  G11C7/22

    摘要： A novel semiconductor memory device includes an address detection circuit that produces a short-width pulse in response to the detection of an address change. A column decoder-activating signal generator detects the start of the short-width pulse and in response generates a column decoder-activating signal. A second detection circuit detects the conclusion of the short-width pulse and generates a second pulse that triggers a preamplifier-activating signal that activates a preamplifier and latches the data that is present on the input/output line. A reset signal generator produces a reset signal to deactivate the column decoder-activating signal and to delay the preamplifier-activating signal. The preamplifier-activating signal generator and the reset signal generator are reset while the first pulse is output.

    摘要翻译： 一种新颖的半导体存储器件包括响应于地址变化的检测而产生短宽度脉冲的地址检测电路。 列解码器激活信号发生器检测短宽度脉冲的开始，并且响应于产生列解码器激活信号。 第二检测电路检测短宽度脉冲的结论，并产生触发前置放大器激活信号的第二脉冲，其激活前置放大器并锁存输入/输出线上存在的数据。 复位信号发生器产生复位信号以停用列解码器激活信号并延迟前置放大器激活信号。 当输出第一个脉冲时，前置放大器激活信号发生器和复位信号发生器被复位。

    Dynamic RAM having full-sized dummy cell
    9.
    发明授权
    Dynamic RAM having full-sized dummy cell 失效
    具有全尺寸虚拟单元的动态RAM

    公开(公告)号：US4734890A

    公开(公告)日：1988-03-29

    申请号：US929369

    申请日：1986-11-12

    申请人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

    发明人： Hideshi Miyatake ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideto Hidaka ,  Katsumi Dosaka ,  Yasuhiro Konishi

    IPC分类号： G11C11/401 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4099 ,  G11C11/40 ,  G11C13/00

    CPC分类号： G11C11/4099 ,  G11C11/4087

    摘要： A dynamic RAM has dummy capacitors (C6, C7) having the same capacitance as a memory capacitor connected to a pair of bit lines (BL1, BL1), respectively. During an active period, respective dummy capacitors (C6, C7) are charged to the H level and L level, which are signal levels of the bit lines (BL1, BL1) and during precharge period, both dummy capacitors are equalized. Since both dummy capacitors (C6, C7) respectively connected to a pair of bit lines (BL1, BL1) are equalized during precharge period, so that the stored charge values of the dummy capacitors (C6, C7) both become the intermediate value of the ground level and supply potential level.

    摘要翻译： 动态RAM分别具有与连接到一对位线（BL1，＆amp;上升和下降B1）的存储电容器相同的电容的虚拟电容器（C6，C7）。 在有效期间，将各个虚拟电容器（C6，C7）充电为位电平（BL1，上升和下降B1）的信号电平的H电平和L电平，并且在预充电期间，两个虚拟电容器被均衡。 由于分别连接到一对位线（BL1，＆lt;上升＆amp; B1）的两个虚拟电容器（C6，C7）在预充电期间均衡，所以虚拟电容器（C6，C7）的存储的电荷值均成为 地面水平和供应潜力水平。

    Semiconductor memory device with active pull up
    10.
    发明授权
    Semiconductor memory device with active pull up 失效
    具有主动上拉功能的半导体存储器件

    公开(公告)号：US4809230A

    公开(公告)日：1989-02-28

    申请号：US938065

    申请日：1986-12-04

    申请人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    发明人： Yasuhiro Konishi ,  Kazuyasu Fujishima ,  Masaki Kumanoya ,  Hideshi Miyatake ,  Hideto Hidaka ,  Katsumi Dosaka

    IPC分类号： G11C11/407 ,  G11C11/34 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/00 ,  G11C7/00 ,  G11C11/40

    CPC分类号： G11C11/4076 ,  G11C11/4094

    摘要： A MOS dynamic type RAM comprises memory cells (10), dummy cells (11), bit line pairs (BL, BL), word lines (WL), dummy word lines (DWL) and sense amplifiers (12). In a non-active cycle, the potentials of each pair of bit lines (BL, BL) are precharged at 1/2 of a supply potential V.sub.CC. Each sense amplifier (12) operates in an active cycle following the non-active cycle, while each active pull-up circuit (13) pulls up the potential of a higher level one of the pair of bit lines to V.sub.CC. This active cycle is defined by an internal RAS internal signal, which is generated by a NAND circuit (27) in response to an external RAS signal and an RPW signal obtained by delaying the external RAS signal by a delay circuit (20) and having a trailing edge obtained by delaying the trailing edge of the external RAS signal by a prescribed period.

    摘要翻译： MOS动态型RAM包括存储单元（10），虚设单元（11），位线对（BL，＆amp; B和B），字线（WL），虚拟字线（DWL）和读出放大器（12）。 在非有效周期中，每对位线（BL，＆amp; B和B）的电位在电源电位VCC的1/2处被预充电。 每个读出放大器（12）在非活动周期之后的有效周期中工作，而每个有源上拉电路（13）将该对位线中较高一级的电位上拉至VCC。 该活动周期由内部RAS内部信号定义，该内部RAS内部信号由NAND电路（27）响应于通过延迟电路（20）延迟外部＆upbar＆R信号而获得的外部＆upbar＆R信号和＆upbar＆R信号产生的内部RAS内部信号， 并且具有通过将外部＆upbar＆R信号的后沿延迟预定周期而获得的后沿。