公开(公告)号：US4908087A

公开(公告)日：1990-03-13

申请号：US332377

申请日：1989-03-31

申请人： Hideyasu Murooka ,  Masayuki Kyooi ,  Osamu Yamada ,  Noriaki Ujiie

发明人： Hideyasu Murooka ,  Masayuki Kyooi ,  Osamu Yamada ,  Noriaki Ujiie

IPC分类号： B32B37/10 ,  B29C37/00 ,  B29C43/20 ,  B29C43/56 ,  B29C70/46 ,  B29K105/06 ,  B29L31/34 ,  B32B15/08 ,  B32B37/00 ,  H05K3/46

CPC分类号： B29C70/46 ,  B29C43/56 ,  H05K3/4611 ,  B29C2791/002 ,  B29C2791/006 ,  B29C37/006 ,  B29L2031/3425 ,  H05K2203/068

摘要： A method and an apparatus of forming a multilayer printed circuit board which can positively remove voids in the prepregs in the printed board and enhance the reliability of the produced printed circuit board and is superior in economy, wherein a laminated assembly of a plurality of printed circuit board components and a plurality of prepregs alternately laminated on each other is sandwiched between upper and lower jig plates, and the laminated assembly sandwiched between the jig plates is clamped between heating plates of a bonding press to heat the assembly to a predetermined temperature, and, thereafter, a pressure is applied to the upper and lower jig plates so as to urge them against each other for bonding the printed circuit board component and the prepregs. An exterior pressurizing means is provided around the printed circuit board components and the prepregs sandwiched between the upper and lower jig plates in order to prevent the molten prepregs from flowing outwardly, thereby raising the fluid pressure of the molten prepregs to squeeze out air bubbles existing in the prepregs.

摘要翻译： 一种形成多层印刷电路板的方法和装置，其可以肯定地去除印刷电路板中的预浸料坯中的空隙，并提高所制造的印刷电路板的可靠性，并且经济性优异，其中多个印刷电路板 夹板组件和交替层叠在一起的多个预浸料坯被夹在上夹具板和下夹具板之间，并且夹在夹具板之间的层叠组件夹在粘合压力机的加热板之间以将组件加热至预定温度， 此后，向上下夹具板施加压力，以便将它们彼此推压以粘合印刷电路板部件和预浸料。 在印刷电路板部件和夹在上夹具板和下夹具板之间的预浸料坯周围设置有外部加压装置，以防止熔融预浸料坯向外流出，从而提高熔融预浸料坯的流体压力以挤出存在于 预浸料

公开(公告)号：US5300735A

公开(公告)日：1994-04-05

申请号：US37543

申请日：1993-03-22

申请人： Hitoshi Yokono ,  Hideo Arima ,  Takashi Inoue ,  Naoya Kitamura ,  Haruhiko Matsuyama ,  Hitoshi Oka ,  Fumio Kataoka ,  Fusaji Shoji ,  Hideyasu Murooka ,  Masayuki Kyooi

发明人： Hitoshi Yokono ,  Hideo Arima ,  Takashi Inoue ,  Naoya Kitamura ,  Haruhiko Matsuyama ,  Hitoshi Oka ,  Fumio Kataoka ,  Fusaji Shoji ,  Hideyasu Murooka ,  Masayuki Kyooi

IPC分类号： H01L21/48 ,  H01L27/01 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46 ,  H05K1/00

CPC分类号： H01L21/4857 ,  H05K3/4647 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/3025 ,  H05K2203/0733 ,  H05K2203/0769 ,  H05K3/108 ,  H05K3/243 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49165

摘要： Described herein are interconnected mutilayer boards and their fabrication processes. Multilayer conductor lines of a skeleton structure are formed by conducting multilayer metallization while including all resist layers and metallic under-conductive layers and then removing the resist layers and metallic under-conductive layers at once. Spaces between the multilayer conductor lines of the skeleton structure are then filled with a solventless varnish so that insulating layers are formed. Modules making use of such interconnected multilayer boards and computers having such modules are also described.

摘要翻译： 这里描述了互连的多层板及其制造工艺。 骨架结构的多层导体线通过导电多层金属化而形成，同时包括所有的抗蚀剂层和金属的低导电层，然后立即去除抗蚀剂层和金属的不良导电层。 然后用无溶剂清漆填充骨架结构的多层导体线之间的空隙，从而形成绝缘层。 还描述了使用这种互连的多层板的模块和具有这种模块的计算机。

公开(公告)号：US5388328A

公开(公告)日：1995-02-14

申请号：US187546

申请日：1994-01-28

申请人： Hitoshi Yokono ,  Hideo Arima ,  Takashi Inoue ,  Naoya Kitamura ,  Haruhiko Matsuyama ,  Hitoshi Oka ,  Fumio Kataoka ,  Fusaji Shoji ,  Hideyasu Murooka ,  Masayuki Kyooi

发明人： Hitoshi Yokono ,  Hideo Arima ,  Takashi Inoue ,  Naoya Kitamura ,  Haruhiko Matsuyama ,  Hitoshi Oka ,  Fumio Kataoka ,  Fusaji Shoji ,  Hideyasu Murooka ,  Masayuki Kyooi

IPC分类号： H01L21/48 ,  H01L27/01 ,  H05K3/10 ,  H05K3/24 ,  H05K3/46

CPC分类号： H01L21/4857 ,  H05K3/4647 ,  H01L2224/1147 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/15312 ,  H01L2924/16152 ,  H01L2924/3025 ,  H05K2203/0733 ,  H05K2203/0769 ,  H05K3/108 ,  H05K3/243 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/49165

摘要： A process for the fabrication of an interconnected multilayer board involves the steps of forming a metallic under-conductive layer on a base substrate, forming a windowed resist layer on the metallic under-conductive layer, filling windows of the resist layer with a conductor by plating thereby forming a conductor layer, forming another windowed resist layer on the conductor layer and filling windows of this resist layer with a conductor by plating, thereby forming a via-hole layer and to provide a two-level structure of the conductor layer and the via-hole layer. Thereafter, the resist layers and portions of the metallic under-conductor layer other than those in contact with a lower face of the conductor constituting the conductor layer are dissolved to form a two-level skeleton structure of conductor lines and spaces within the skeleton structure are filled with a varnish in a solventless form and the varnish is cured.

摘要翻译： 制造相互连接的多层板的方法包括以下步骤：在基底基板上形成金属导电层，在金属下导电层上形成窗口化抗蚀剂层，用导体用电镀填充抗蚀剂层的窗口 从而形成导体层，在导体层上形成另一个窗口化的抗蚀剂层，并通过电镀用导体填充该抗蚀剂层的窗口，从而形成通孔层，并提供导体层和通孔的两层结构 井层。 此后，除了与形成导体层的导体的下表面接触的金属下导体层的抗蚀剂层和部分被溶解以形成骨架结构内的导体线和空间的两级骨架结构 填充无溶剂形式的清漆，并且清漆被固化。

公开(公告)号：US5182121A

公开(公告)日：1993-01-26

申请号：US594711

申请日：1990-10-09

申请人： Akimi Miyashita ,  Mutsumasa Fujii ,  Minoru Kubosawa ,  Keiichiro Torii ,  Nobuaki Ooki ,  Kiyonori Kogawa ,  Masami Kawaguchi ,  Hideyasu Murooka ,  Masayuki Kyooi

发明人： Akimi Miyashita ,  Mutsumasa Fujii ,  Minoru Kubosawa ,  Keiichiro Torii ,  Nobuaki Ooki ,  Kiyonori Kogawa ,  Masami Kawaguchi ,  Hideyasu Murooka ,  Masayuki Kyooi

IPC分类号： B30B7/02 ,  B29C33/04 ,  B29C43/20 ,  B29C43/32 ,  B29C43/56 ,  B29C65/52 ,  B29C65/78 ,  B29L9/00 ,  B30B12/00 ,  B30B15/00 ,  B30B15/34 ,  H05K3/46

CPC分类号： B30B15/0017 ,  B29C33/04 ,  B29C43/56 ,  B29C2043/561 ,  B29C43/32 ,  H05K3/4611

摘要： A hot press including a displaceable sleeve for surrounding materials of a multi-layer substrate under a reduced pressure condition, a gas pressurizing condition and a heating condition with thermal plates. Upper and lower sealing units seal an interior of the sleeve, with a mechanism lowering and raising the sleeve. A pilot check mechanism prevents a lower bolster from raising/lowering upon the reduced pressure condition and the gas pressure condition, and a retainer maintains the lowered or raised condition of the sleeve. The multi-layer substrate is formed under the reduced pressure condition and the gas pressure condition. Accordingly, the atmosphere and moisture between the materials of the multi-layer substrate and volatile composition are removed. Additionally, a void generated during the heat and pressure process by the heating plates is eliminated from the multi-layer substrate. By carrying out the formation of the multi-layer substrate at the heat and pressure by the heating plates under the gas pressure condition, a final dimensional precision and shape are enhanced and a warpage or twist is suppressed.

摘要翻译： 一种热压机，包括用于在减压条件下的多层基板的周围材料的可置换套筒，气体加压条件和具有热板的加热条件。 上下密封单元密封套筒的内部，机构降低并提升套筒。 先导检查机构防止下压板在减压条件和气压条件下升高/降低，并且保持器保持套筒的降低或升高的状态。 在减压条件和气体压力条件下形成多层基板。 因此，除去多层基材的材料和挥发性组合物之间的气氛和水分。 此外，在多层基板中消除了在加热板的加热和加压过程期间产生的空隙。 通过在气体压力条件下通过加热板在热和压力下进行多层基板的形成，提高了最终的尺寸精度和形状，并且抑制了翘曲或扭曲。

公开(公告)号：US06506982B1

公开(公告)日：2003-01-14

申请号：US09501596

申请日：2000-02-10

申请人： Hidetaka Shigi ,  Naoya Kitamura ,  Masashi Nishiki ,  Tetsuya Yamazaki ,  Takehiko Hasebe ,  Masayuki Kyooi ,  Yukio Maeda

发明人： Hidetaka Shigi ,  Naoya Kitamura ,  Masashi Nishiki ,  Tetsuya Yamazaki ,  Takehiko Hasebe ,  Masayuki Kyooi ,  Yukio Maeda

IPC分类号： H05K111

CPC分类号： H05K3/403 ,  H01L2224/16237 ,  H05K1/056 ,  H05K3/045 ,  H05K3/42 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2201/09809 ,  H05K2201/09854

摘要： A multi-layer wiring substrate capable of high density packaging, and a method of manufacturing the same, in which a carrier substrate, in which through holes can be easily formed in high density corresponding substantially to a pitch of connecting terminals in a semiconductor chip, and build-up layers are formed on the substrate with the application of a conventional build-up technique. When the build-up technique for repeatedly forming insulating layers and wiring layers on a carrier substrate is used to manufacture a multi-layer wiring substrate, the carrier substrate is formed in the following manner. First, an insulating resin layer is formed in a copper foil, in which a plurality of first windows are regularly provided, to cover the copper foil, and the resin layer fills the interior of the windows. Subsequently, second windows of a particular shape are provided in regions of layers of the insulating resin filled in the windows, and independent conducting paths are formed through the second windows to extend from front sides of the second windows to back sides thereof. The conducting paths are formed radially to be spaced a substantially equal distance from centers of the respective second windows.