公开(公告)号：US20090134431A1

公开(公告)日：2009-05-28

申请号：US12275794

申请日：2008-11-21

申请人： Hideyuki TABATA ,  Hiroyuki NAGASHIMA ,  Hirofumi INOUE ,  Kohichi KUBO ,  Masanori KOMURA

发明人： Hideyuki TABATA ,  Hiroyuki NAGASHIMA ,  Hirofumi INOUE ,  Kohichi KUBO ,  Masanori KOMURA

IPC分类号： H01L29/66 ,  H01L29/00 ,  H01L21/20

CPC分类号： H01L45/1675 ,  G11C13/00 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2481 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147

摘要： A nonvolatile semiconductor storage apparatus includes: a plurality of first wirings; a plurality of second wirings which cross the plurality of first wirings; and a memory cell which is connected between both the wirings at an intersection of the first and second wirings, and includes a variable resistive element operative to store information according to a change in resistance and includes a variable resistive element, wherein the memory cell is formed so that a cross section area of the variable resistive element becomes smaller than a cross section area of the other portion.

摘要翻译： 非易失性半导体存储装置包括：多个第一布线; 跨过多个第一配线的多个第二配线; 以及存储单元，其连接在所述第一和第二布线的交叉点处的所述布线之间，并且包括可变电阻元件，用于根据电阻变化存储信息，并且包括可变电阻元件，其中形成所述存储单元 使得可变电阻元件的横截面面积变得小于另一部分的横截面面积。

公开(公告)号：US20120205612A1

公开(公告)日：2012-08-16

申请号：US13454625

申请日：2012-04-24

申请人： Hideyuki TABATA ,  Eiji ITO ,  Hirofumi INOUE

发明人： Hideyuki TABATA ,  Eiji ITO ,  Hirofumi INOUE

IPC分类号： H01L45/00 ,  H01L21/8239

CPC分类号： H01L27/2481 ,  G11C13/00 ,  G11C13/0009 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile semiconductor memory device comprises a semiconductor substrate; a cell array block formed on the semiconductor substrate and including plural stacked cell array layers each with a plurality of first lines, a plurality of second lines crossing the plurality of first lines, and memory cells connected at intersections of the first and second lines between both lines; and a plurality of via-holes extending in the stacked direction of the cell array layers to individually connect the first or second line in the each cell array layer to the semiconductor substrate. The via-holes are formed continuously through the plural cell array layers, and multiple via-holes having equal lower end positions and upper end positions are connected to the first or second lines in different cell array layers.

摘要翻译： 非易失性半导体存储器件包括半导体衬底; 形成在所述半导体衬底上的单元阵列块，并且包括多个堆叠的单元阵列层，每个堆叠的单元阵列层具有多个第一线，与所述多条第一线交叉的多个第二线，以及在所述第一和第二线的两个交点处连接的存储单元 线条 以及在单元阵列层的堆叠方向上延伸的多个通孔，以将每个单元阵列层中的第一或第二线分别连接到半导体基板。 通孔连续地形成在多个单元阵列层中，并且具有相同的下端位置和上端位置的多个通孔与不同的单元阵列层中的第一或第二线连接。

公开(公告)号：US20110241225A1

公开(公告)日：2011-10-06

申请号：US13158098

申请日：2011-06-10

申请人： Hiroyuki NAGASHIMA ,  Hirofumi INOUE

发明人： Hiroyuki NAGASHIMA ,  Hirofumi INOUE

IPC分类号： H01L23/48

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

摘要翻译： 一种半导体存储器件包括具有堆叠存储单元阵列的三维存储单元阵列结构的存储块，所述存储单元阵列包括：彼此平行的多个第一互连; 多个第二互连形成为与所述多个第一互连相交，所述第二互连彼此平行; 以及存储单元，其设置在所述第一互连和所述第二互连的每个交叉部分中，所述存储单元的一端连接到所述第一互连，所述存储单元的另一端连接到所述第二互连。 设置在相邻存储单元阵列之间的第一互连由第一互连之上和之下的存储单元共享，并且垂直重叠的第一互连彼此连接。

公开(公告)号：US20090141532A1

公开(公告)日：2009-06-04

申请号：US12325040

申请日：2008-11-28

申请人： Hiroyuki NAGASHIMA ,  Hirofumi INOUE

发明人： Hiroyuki NAGASHIMA ,  Hirofumi INOUE

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C8/14 ,  G11C5/02 ,  G11C5/063 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C2213/31 ,  G11C2213/71 ,  G11C2213/72 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor memory device includes a memory block having a three-dimensional memory cell array structure in which memory cell arrays are stacked, the memory cell array including: a plurality of first interconnections which are parallel to one another; a plurality of second interconnections which are formed so as to intersect with the plurality of first interconnections, the second interconnections being parallel to one another; and a memory cell which is disposed in each intersection portion of the first interconnection and the second interconnection, one end of the memory cell being connected to the first interconnection, the other end of the memory cell being connected to the second interconnection. The first interconnection disposed between the adjacent memory cell arrays is shared by memory cells above and below the first interconnection, and the vertically-overlapping first interconnections are connected to each other.

摘要翻译： 一种半导体存储器件包括具有堆叠存储单元阵列的三维存储单元阵列结构的存储块，所述存储单元阵列包括：彼此平行的多个第一互连; 多个第二互连形成为与所述多个第一互连相交，所述第二互连彼此平行; 以及存储单元，其设置在所述第一互连和所述第二互连的每个交叉部分中，所述存储单元的一端连接到所述第一互连，所述存储单元的另一端连接到所述第二互连。 设置在相邻存储单元阵列之间的第一互连由第一互连之上和之下的存储单元共享，并且垂直重叠的第一互连彼此连接。

公开(公告)号：US20100238702A1

公开(公告)日：2010-09-23

申请号：US12559931

申请日：2009-09-15

申请人： Takeshi YAMAGUCHI ,  Mariko HAYASHI ,  Hirofumi INOUE ,  Takeshi ARAKI ,  Koichi KUBO

发明人： Takeshi YAMAGUCHI ,  Mariko HAYASHI ,  Hirofumi INOUE ,  Takeshi ARAKI ,  Koichi KUBO

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/33 ,  G11C2213/71 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/1021

摘要： A memory array includes a memory cell, the memory cell being disposed between a first line and a second line and being configured by a variable resistor and a rectifier connected in series. The variable resistor is a mixture of silicon oxide (SiO2) and a transition metal oxide, a proportion of the transition metal oxide being set to 55˜80%.

摘要翻译： 存储器阵列包括存储器单元，存储单元设置在第一线路和第二线路之间，并且由可变电阻器和串联连接的整流器构成。 可变电阻器是氧化硅（SiO 2）和过渡金属氧化物的混合物，过渡金属氧化物的比例设定为55〜80％。

公开(公告)号：US20080099819A1

公开(公告)日：2008-05-01

申请号：US11874004

申请日：2007-10-17

申请人： Masaru KITO ,  Hirofumi INOUE

发明人： Masaru KITO ,  Hirofumi INOUE

IPC分类号： H01L29/788 ,  H01L21/8239 ,  H01L21/8247

CPC分类号： H01L27/105 ,  G11C16/10 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582

摘要： According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage apparatus including: a substrate; a columnar semiconductor disposed perpendicular to the substrate; a charge storage laminated film disposed around the columnar semiconductor; a first conductor layer that is in contact with the charge storage laminated film and that has a first end portion having a first end face; a second conductor layer that is in contact with the charge storage laminated film, that is separated from the first conductor layer and that has a second end portion having a second end face; a first contact plug disposed on the first end face; and a second contact plug disposed on the second end face.

摘要翻译： 根据本发明的一个方面，提供了一种非易失性半导体存储装置，包括：基板; 垂直于衬底设置的柱状半导体; 设置在所述柱状半导体周围的电荷存储层叠膜; 与所述电荷存储叠层膜接触并具有第一端部的第一导体层，所述第一端部具有第一端面; 与电荷存储叠层膜接触的第二导体层，其与第一导体层分离并且具有具有第二端面的第二端部; 设置在所述第一端面上的第一接触插塞; 以及设置在所述第二端面上的第二接触插塞。