公开(公告)号：US5930599A

公开(公告)日：1999-07-27

申请号：US40304

申请日：1998-03-18

申请人： Hiroaki Fujimoto ,  Shinitsu Takehashi ,  Takashi Ohtsuka

发明人： Hiroaki Fujimoto ,  Shinitsu Takehashi ,  Takashi Ohtsuka

IPC分类号： H01L21/56 ,  H01L21/98 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/181 ,  H01L2924/351

摘要： A semiconductor device comprises a square-shaped first semiconductor chip having a first LSI, a square-shaped second semiconductor chip having a second LSI, which is smaller in size than the first semiconductor chip and connected to the first semiconductor chip by face down bonding, and a square-shaped package made of a molding resin for packaging the first and second semiconductor chips. The respective centers of the first and second semiconductor chips are offset from each other, while the center of the second semiconductor chip is substantially coincident with the center of the molding resin.

摘要翻译： 一种半导体器件包括具有第一LSI的正方形的第一半导体芯片，具有第二LSI的方形第二半导体芯片，其尺寸小于第一半导体芯片，并且通过面朝下接合连接到第一半导体芯片， 以及由用于封装第一和第二半导体芯片的模制树脂制成的方形封装。 第一半导体芯片和第二半导体芯片的各个中心彼此偏移，而第二半导体芯片的中心与模制树脂的中心基本一致。

公开(公告)号：US5773896A

公开(公告)日：1998-06-30

申请号：US802025

申请日：1997-02-18

申请人： Hiroaki Fujimoto ,  Shinitsu Takehashi ,  Takashi Ohtsuka

发明人： Hiroaki Fujimoto ,  Shinitsu Takehashi ,  Takashi Ohtsuka

IPC分类号： H01L21/56 ,  H01L21/98 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065 ,  H01L23/48 ,  H01L23/34

CPC分类号： H01L25/50 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49861 ,  H01L24/29 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06582 ,  H01L2225/06596 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/181 ,  H01L2924/351

摘要： A semiconductor device comprises a square-shaped first semiconductor chip having a first LSI, a square-shaped second semiconductor chip having a second LSI, which is smaller in size than the first semiconductor chip and connected to the first semiconductor chip by face down bonding, and a square-shaped package made of a molding resin for packaging the first and second semiconductor chips. The respective centers of the first and second semiconductor chips are offset from each other, while the center of the second semiconductor chip is substantially coincident with the center of the molding resin.

摘要翻译： 一种半导体器件包括具有第一LSI的正方形的第一半导体芯片，具有第二LSI的方形第二半导体芯片，其尺寸小于第一半导体芯片，并且通过面朝下接合连接到第一半导体芯片， 以及由用于封装第一和第二半导体芯片的模制树脂制成的方形封装。 第一半导体芯片和第二半导体芯片的各个中心彼此偏移，而第二半导体芯片的中心与模制树脂的中心基本一致。

公开(公告)号：US5952718A

公开(公告)日：1999-09-14

申请号：US804968

申请日：1997-02-24

申请人： Takashi Ohtsuka ,  Tetsuo Kawakita ,  Kazuhiko Matsumura ,  Hiroaki Fujimoto

发明人： Takashi Ohtsuka ,  Tetsuo Kawakita ,  Kazuhiko Matsumura ,  Hiroaki Fujimoto

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/485 ,  H01L23/48

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L24/11 ,  H01L24/29 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/7525 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/15788

摘要： A semiconductor device having a protection layer covering the active layer of a semiconductor chip with an opening therein corresponding in location to a chip electrode located on the active surface of the semiconductor chip. Inside the opening a barrier layer covers the chip electrode, a diffusion barrier layer covers the barrier layer and a protruding contact protruding from the diffusion barrier layer. The protruding contact preferably comprises material whose hardness is lower than that of each of the barrier layer and chip electrode.

摘要翻译： 一种半导体器件，其具有覆盖半导体芯片的有源层的保护层，其中位于半导体芯片的有源表面上的与芯片电极相对应的开口。 在所述开口内，阻挡层覆盖所述芯片电极，扩散阻挡层覆盖所述阻挡层和从所述扩散阻挡层突出的突出接触。 突出接触件优选包括其硬度低于阻挡层和芯片电极的硬度的材料。

公开(公告)号：US06107120A

公开(公告)日：2000-08-22

申请号：US275185

申请日：1999-03-23

申请人： Takashi Ohtsuka ,  Tetsuo Kawakita ,  Kazuhiko Matsumura ,  Hiroaki Fujimoto

发明人： Takashi Ohtsuka ,  Tetsuo Kawakita ,  Kazuhiko Matsumura ,  Hiroaki Fujimoto

IPC分类号： H01L21/60 ,  H01L21/56 ,  H01L23/485 ,  H01L21/44 ,  H01L21/50

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L24/11 ,  H01L24/29 ,  H01L24/75 ,  H01L24/83 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/13155 ,  H01L2224/13609 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/75 ,  H01L2224/7525 ,  H01L2224/75252 ,  H01L2224/75301 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/83102 ,  H01L2224/83192 ,  H01L2224/83874 ,  H01L2224/92125 ,  H01L2924/0001 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/15788

摘要： A method of making semiconductor devices with contacts protruding from openings in a passivation layer over an active chip area. Inside each opening, a relatively hard barrier layer is provided and a flash-plated film is applied to subsequently form a relatively soft diffusion barrier layer when a protruding contact is formed. Two semiconductor devices with electrodes are joined by embedding relatively hard electrodes of a first device into relatively soft electrodes of a second device. A reducing agent can be incorporated into an insulating resin applied between semiconductor chips at areas other than the bonded electrodes.

摘要翻译： 一种制造半导体器件的方法，其具有从有源芯片区域上的钝化层中的开口突出的触点。 在每个开口内部，设置相对硬的阻挡层，并且当形成突出接触​​时，施加闪镀膜以随后形成相对软的扩散阻挡层。 具有电极的两个半导体器件通过将第一器件的相对硬的电极嵌入到第二器件的相对软的电极中来连接。 还原剂可以结合到施加在不同于键合电极之外的区域的半导体芯片之间的绝缘树脂中。

公开(公告)号：US20100328894A1

公开(公告)日：2010-12-30

申请号：US12865780

申请日：2009-02-16

申请人： Mikio Oda ,  Tomotaka Ishida ,  Hisaya Takahashi ,  Hideyuki Ono ,  Jun Sakai ,  Takashi Ohtsuka ,  Arihide Noda ,  Hikaru Kouta

发明人： Mikio Oda ,  Tomotaka Ishida ,  Hisaya Takahashi ,  Hideyuki Ono ,  Jun Sakai ,  Takashi Ohtsuka ,  Arihide Noda ,  Hikaru Kouta

IPC分类号： H05K7/20 ,  G02B6/36

CPC分类号： H01L25/167 ,  G02B6/4201 ,  G02B6/4257 ,  G02B6/4266 ,  G02B6/4274 ,  H01L2924/0002 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/00

摘要： Provided is an optical interconnection device in which a volume required for cooling is reduced. In the optical interconnection device, a plurality of optical modules (12) are arranged on a periphery of an LSI (11) electrically connected to an electric wiring board (10), and liquid cooling mechanisms (13, 14) are respectively placed on the LSI (11) and the optical modules (12). The plurality of optical modules (12) may be arranged only on a surface of the electric wiring board (10) where the LSI (11) is mounted, only on a surface opposite to the surface where the LSI (11) is mounted, or on both the same surface as and the opposite surface to the surface where the LSI (11) is mounted.

摘要翻译： 提供一种其中冷却所需的体积减小的光学互连装置。 在光互连装置中，在与电气布线板（10）电连接的LSI（11）的周围配置多个光模块（12），液体冷却机构（13,14）分别置于 LSI（11）和光模块（12）。 多个光学模块（12）可以仅布置在安装有LSI（11）的电气布线板（10）的仅在与安装LSI（11）的表面相对的表面上，或者 在与安装LSI（11）的表面相同的表面上和相对的表面上。

公开(公告)号：US20100098383A1

公开(公告)日：2010-04-22

申请号：US12449174

申请日：2008-01-21

申请人： Yuichi Koreeda ,  Wataru Ohtsu ,  Mikio Oda ,  Hisaya Takahashi ,  Takashi Ohtsuka ,  Hikaru Kouta ,  Hideyuki Ono

发明人： Yuichi Koreeda ,  Wataru Ohtsu ,  Mikio Oda ,  Hisaya Takahashi ,  Takashi Ohtsuka ,  Hikaru Kouta ,  Hideyuki Ono

IPC分类号： G02B6/36

CPC分类号： G02B6/4292 ,  G02B6/4284

摘要： In a photoelectric conversion/connection device (100) including an optical element (320), a mounting board (310) on which the optical element is mounted, and an optical connector (400) which is connected to the mounting board so as to be optically connected to the optical element, the optical connector (400) is arranged on a surface (310a) opposite to a mounting surface (310b) of the mounting board (310) and the optical element (320) is exposed. The photoelectric conversion/connection device (100) includes a motherboard (210) having a main surface (210a) and an electric connector (220) to be mounted on the main surface of the motherboard. The electric connector (220) is detachably connected to the mounting board (310).

摘要翻译： 在包括光学元件（320）的光电转换/连接装置（100），安装有光学元件的安装板（310）和连接到安装板的光连接器（400） 光连接到光学元件，光连接器（400）布置在与安装板（310）的安装表面（310b）相对的表面（310a）上，并且光学元件（320）被暴露。 光电转换/连接装置（100）包括具有主表面（210a）的主板（210）和安装在母板主表面上的电连接器（220）。 电连接器（220）可拆卸地连接到安装板（310）。

公开(公告)号：US06980043B2

公开(公告)日：2005-12-27

申请号：US11052794

申请日：2005-02-09

申请人： Kenji Toyoda ,  Takashi Ohtsuka

发明人： Kenji Toyoda ,  Takashi Ohtsuka

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/866 ,  H03K17/62

CPC分类号： G11C11/22

摘要： A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor or a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1) comprises is applied to said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor (1).

摘要翻译： 一种铁电栅极器件，包括铁电电容器（1），用作电阻器的开关元件（2）或取决于所施加的电压的电容器;以及具有源极，漏极和栅极的场效应晶体管 所述铁电电容器（1）的一端具有输入端（IN），所述铁电电容器（1）的另一端与所述开关元件（2）的一端连接，所述开关元件（2）的另一端 ）通过向所述输入端子施加电压而连接到所述场效应晶体管（6）的栅极，所述开关元件（2）在高于铁电体的矫顽电压（Vc）的电压时用作电阻器 所述铁电电容器（1）包括的所述铁电电容器（1）被施加到所述铁电电容器（1），并且通过向所述输入端子施加电压，所述开关元件（2）当电压低于所述铁电电容器（1）的矫顽电压 说ferroelec 三体物质被施加到所述铁电电容器（1）。

公开(公告)号：US06949780B2

公开(公告)日：2005-09-27

申请号：US10847323

申请日：2004-05-18

申请人： Michihito Ueda ,  Kenji Toyoda ,  Kiyoyuki Morita ,  Takashi Ohtsuka

发明人： Michihito Ueda ,  Kenji Toyoda ,  Kiyoyuki Morita ,  Takashi Ohtsuka

IPC分类号： H01L27/10 ,  G11C27/00 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： G11C27/005 ,  G11C11/54 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an electric potential generating device, a source of an N type MIS transistor is mutually connected to that of a P type MIS transistor and also connected to an output terminal. A drain of an N type MIS transistor 54 is connected to a power supply voltage supply portion for supplying power supply voltage VDD, and a drain of the P type MIS transistor is connected to a ground. In addition, a substrate potential of the N type MIS transistor is a ground voltage VSS, and that of a P type MIS transistor 56 is the power supply voltage VDD. Thus, it is constituted as a source follower circuit for taking output out of the source. It is possible, by utilizing this electric potential generating device, to obtain a logic transformation circuit for stably switching between NOR operation and NAND operation.

公开(公告)号：US06859088B2

公开(公告)日：2005-02-22

申请号：US10716670

申请日：2003-11-20

申请人： Kenji Toyoda ,  Takashi Ohtsuka

发明人： Kenji Toyoda ,  Takashi Ohtsuka

IPC分类号： G11C11/22 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/866 ,  H03K17/62 ,  H03K17/687

CPC分类号： G11C11/22

摘要： A ferroelectric gate device which comprises a ferroelectric capacitor (1), a switching element (2) serving as a resistor of a capacitor depending on the voltage applied, and a field-effect transistor (6) having a source, a drain and a gate, said ferroelectric capacitor (1) having an input terminal (IN) at one end, the other end of said ferroelectric capacitor (1) being connected to one end of said switching element (2), the other end of said switching element (2) being connected to the gate of said field-effect transistor (6), by applying a voltage to said input terminal, said switching element (2) serving as a resistor when a voltage higher than the coercive voltage (Vc) of a ferroelectric substance which said ferroelectric capacitor (1), and by applying a voltage to said input terminal, said switching element (2) serving as a capacitor when a voltage lower than the coercive voltage (Vc) of said ferroelectric substance is applied to said ferroelectric capacitor (1).

摘要翻译： 一种强电介质栅极器件，包括铁电电容器（1），根据施加的电压用作电容器的电阻器的开关元件（2）和具有源极，漏极和栅极的场效应晶体管 所述铁电电容器（1）的一端具有输入端（IN），所述铁电电容器（1）的另一端与所述开关元件（2）的一端连接，所述开关元件（2）的另一端 ）通过向所述输入端子施加电压而连接到所述场效应晶体管（6）的栅极，所述开关元件（2）在高于铁电体的矫顽电压（Vc）的电压时用作电阻器 所述铁电电容器（1），并且当低于所述铁电体的矫顽电压（Vc）的电压施加到所述铁电电容器时，所述开关元件（2）作为电容器施加电压到所述输入端子， 1）。

公开(公告)号：US06720288B1

公开(公告)日：2004-04-13

申请号：US10069032

申请日：2002-05-28

申请人： Masahiro Kanayama ,  Tsutomu Mabuchi ,  Takashi Ohtsuka ,  Sumitaka Kose

发明人： Masahiro Kanayama ,  Tsutomu Mabuchi ,  Takashi Ohtsuka ,  Sumitaka Kose

IPC分类号： A01N4356

CPC分类号： A01N43/56 ,  A01N57/20 ,  A01N61/00 ,  A01N57/00 ,  A01N25/30 ,  A01N57/18 ,  A01N57/02 ,  A01N2300/00

摘要： Herbicidal compositions containing as the active ingredients (one or more compounds selected from among light-induced herbicidal compounds and one or more compounds selected from among organoposphorus herbicidal compounds, characterized by containing ethylenediamine alkoxylates and alcohol alkoxylates as surfactants. These herbicidal compositions have an excellent rapid action and exert a remarkable herbicidal effect in a small dose.

摘要翻译： 含有作为活性成分的一种或多种化合物（一种或多种选自光诱导的除草化合物和一种或多种选自有机磷除草化合物的化合物的化合物，其特征在于含有乙二胺烷氧基化物和醇烷氧基化物作为表面活性剂，这些除草组合物具有极好的快速 作用并以小剂量发挥显着的除草效果。