公开(公告)号：US20050048768A1

公开(公告)日：2005-03-03

申请号：US10924767

申请日：2004-08-25

申请人： Hiroaki Inoue ,  Yukio Fukunaga ,  Akira Susaki

发明人： Hiroaki Inoue ,  Yukio Fukunaga ,  Akira Susaki

IPC分类号： H01L21/00 ,  H01L21/288 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76843 ,  H01L21/02052 ,  H01L21/288 ,  H01L21/32134 ,  H01L21/6708 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76877 ,  H01L2221/1089

摘要： There is provided an apparatus for forming interconnects which can form embedded interconnects or interconnects protected with a protective film while preventing the formation of an oxide film. An interconnects-forming apparatus for forming embedded interconnects in a surface of a substrate, includes: a barrier layer-forming apparatus for forming a barrier layer on a surface of a substrate; a metal layer-forming apparatus for forming a metal layer on the surface of the barrier layer formed in the barrier layer-forming apparatus; and an apparatus frame capable of controlling the internal atmosphere; wherein the barrier layer-forming apparatus and the metal layer-forming apparatus are disposed in the apparatus frame.

摘要翻译： 提供了一种用于形成互连的装置，其可以形成用保护膜保护的嵌入式互连或互连，同时防止氧化膜的形成。 一种用于在衬底的表面中形成嵌入式互连的互连形成装置，包括：阻挡层形成装置，用于在衬底的表面上形成阻挡层; 金属层形成装置，用于在阻挡层形成装置中形成的势垒层的表面上形成金属层; 以及能够控制内部气氛的装置框架; 其中所述阻挡层形成装置和所述金属层形成装置设置在所述装置框架中。

公开(公告)号：US20050029669A1

公开(公告)日：2005-02-10

申请号：US10893244

申请日：2004-07-19

申请人： Hiroaki Inoue ,  Akira Susaki

发明人： Hiroaki Inoue ,  Akira Susaki

IPC分类号： C23C18/16 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52

CPC分类号： H01L21/76885 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device including a highly reliable multi-level interconnect structure having a low effective dielectric constant and which can be easily manufactured with a relatively inexpensive process, and a method for manufacturing the semiconductor device. The semiconductor device includes a lower-level interconnect and an upper-level interconnect, each surrounded by a barrier layer, and a via plug surrounded by a barrier layer and electrically connecting the lower-level interconnect and the upper-level interconnect.

摘要翻译： 一种半导体器件，包括具有低有效介电常数的高可靠性多电平互连结构，并且可以以相对便宜的工艺容易地制造，以及半导体器件的制造方法。 该半导体器件包括一个下层互连和一个上层互连，每一个都被一个阻挡层包围，一个由阻挡层包围并通过电气连接下层互连和上层互连的通孔。

公开(公告)号：US07157370B2

公开(公告)日：2007-01-02

申请号：US10893244

申请日：2004-07-19

申请人： Hiroaki Inoue ,  Akira Susaki

发明人： Hiroaki Inoue ,  Akira Susaki

IPC分类号： H01L21/4763

CPC分类号： H01L21/76885 ,  H01L21/76852 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a highly reliable multi-level interconnect structure having a low effective dielectric constant and which can be easily manufactured with a relatively inexpensive process, and a method for manufacturing the semiconductor device. The semiconductor device includes a lower-level interconnect and an upper-level interconnect, each surrounded by a barrier layer, and a via plug surrounded by a barrier layer and electrically connecting the lower-level interconnect and the upper-level interconnect.

摘要翻译： 半导体器件包括具有低有效介电常数并且可以以相对便宜的工艺容易地制造的高可靠性多电平互连结构，以及用于制造半导体器件的方法。 该半导体器件包括一个下层互连和一个上层互连，每一个都被一个阻挡层包围，一个由阻挡层包围并通过电气连接下层互连和上层互连的通孔。

公开(公告)号：US07413983B2

公开(公告)日：2008-08-19

申请号：US10864496

申请日：2004-06-10

申请人： Hiroaki Inoue ,  Akira Susaki

发明人： Hiroaki Inoue ,  Akira Susaki

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  C23C18/1607 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/1841 ,  C23C18/1844 ,  C23C18/32 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76874

摘要： The present invention provides a plating method and a plating apparatus which can securely form a metal film (protective film) by electroless plating on the exposed surfaces of a base metal, such as interconnects without the formation of voids in the base metal. The plating method including providing a semiconductor device having an embedded interconnect structure, carrying out pretreatment of interconnects with a pre-treatment liquid containing a surface activating agent for the interconnects, carrying out catalytic treatment of the interconnects with a catalytic treatment liquid containing catalyst metal ions and an excessive etching inhibitor for the interconnects, and forming a protective film by electroless plating selectively on the surfaces of the interconnects.

摘要翻译： 本发明提供了一种电镀方法和电镀装置，其可以通过无电镀在基体金属的露出表面如互连而牢固地形成金属膜（保护膜），而不会在基体金属中形成空隙。 电镀方法包括提供具有嵌入式互连结构的半导体器件，对包含用于互连的表面活化剂的预处理液进行互连的预处理，对含有催化剂金属离子的催化处理液进行互连的催化处理 以及用于互连的过量的蚀刻抑制剂，并且通过在互连的表面上选择性地通过无电镀形成保护膜。

公开(公告)号：US20050069646A1

公开(公告)日：2005-03-31

申请号：US10864496

申请日：2004-06-10

申请人： Hiroaki Inoue ,  Akira Susaki

发明人： Hiroaki Inoue ,  Akira Susaki

IPC分类号： C23C18/16 ,  C23C18/18 ,  C23C18/32 ,  C23C18/50 ,  H01L21/288 ,  H01L21/768 ,  B05D3/04 ,  B05D3/10 ,  H01L21/44

CPC分类号： H01L21/76849 ,  C23C18/1607 ,  C23C18/1831 ,  C23C18/1834 ,  C23C18/1841 ,  C23C18/1844 ,  C23C18/32 ,  C23C18/50 ,  H01L21/288 ,  H01L21/76874

摘要： The present invention provides a plating method and a plating apparatus which can securely form a metal film (protective film) by electroless plating on the exposed surfaces of a base metal, such as interconnects without the formation of voids in the base metal. The plating method including providing a semiconductor device having an embedded interconnect structure, carrying out pretreatment of interconnects with a pre-treatment liquid containing a surface activating agent for the interconnects, carrying out catalytic treatment of the interconnects with a catalytic treatment liquid containing catalyst metal ions and an excessive etching inhibitor for the interconnects, and forming a protective film by electroless plating selectively on the surfaces of the interconnects.

摘要翻译： 本发明提供了一种电镀方法和电镀装置，其可以通过无电镀在基体金属的露出表面如互连而牢固地形成金属膜（保护膜），而不会在基体金属中形成空隙。 电镀方法包括提供具有嵌入式互连结构的半导体器件，对包含用于互连的表面活化剂的预处理液进行互连的预处理，对含有催化剂金属离子的催化处理液进行互连的催化处理 以及用于互连的过量的蚀刻抑制剂，并且通过在互连的表面上选择性地通过无电镀形成保护膜。

公开(公告)号：US09553604B2

公开(公告)日：2017-01-24

申请号：US13262181

申请日：2010-03-19

申请人： Hiroaki Inoue

发明人： Hiroaki Inoue

IPC分类号： H03M7/30 ,  G11C7/10 ,  H04L29/12 ,  G11C29/00

CPC分类号： H03M7/30 ,  G11C7/103 ,  G11C29/003 ,  H04L29/12311

摘要： In order to improve the compression rate for configuration information including address information and data information when transmitting or storing configuration information which includes addresses and data having differing characteristics, an information compression device is provided with a compressor which receives as input and compresses the configuration information provided with the addresses and data, and a compressed information storage module for storing the configuration information which is compressed, that is, compressed configuration information, as the information to be decompressed for the user, said compressor including an information separating module for separating the configuration information into address information and data information, an address compressor and data compressor which separately compress the separated address information and data information, and a compressed information outputting module for combining the compressed address information and data information and outputting the result as compressed configuration information.

摘要翻译： 为了在发送或存储具有不同特征的地址和数据的配置信息的情况下提高包括地址信息和数据信息的配置信息的压缩率，信息压缩装置设置有作为输入接收并压缩提供的配置信息的压缩器 具有地址和数据的压缩信息存储模块，以及用于将被压缩的配置信息（即，压缩配置信息）存储为要为用户解压缩的信息的压缩信息存储模块，所述压缩器包括用于分离配置信息的信息分离模块 地址信息和数据信息，分离地压缩分离的地址信息和数据信息的地址压缩器和数据压缩器，以及压缩信息输出模块，用于将压缩的地址信息和数据 信息并将结果作为压缩配置信息输出。

公开(公告)号：US09164905B2

公开(公告)日：2015-10-20

申请号：US13393814

申请日：2010-08-18

申请人： Hiroaki Inoue

发明人： Hiroaki Inoue

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0802 ,  G06F2212/1028 ,  Y02D10/13

摘要： There are provided a semiconductor integrated circuit device, a method of controlling a semiconductor integrated circuit device, and a cache device capable of efficiently implementing power saving, wherein the cache device includes a low-voltage operation enabling cache (200), and a small-area cache (300) having a type different from that of the cache (200), the cache (200) and the cache (300) being independently supplied with source voltage; the cache (200) being operable at a voltage lower than the lower limit voltage at which the cache (300) is operable; a cache control unit (400) operating switchable controls between a first mode allowing only the cache (200) to operate, and a second mode allowing the cache (200) or the cache (300) to operate; and the cache (200) in the first mode operating to supply a voltage below the lower limit voltage at which the cache (300) is operable, while interrupting power supply to the cache (300).

摘要翻译： 提供了一种半导体集成电路器件，一种半导体集成电路器件的控制方法和能够有效地实现功率节省的高速缓存器件，其中该高速缓存器件包括一个使能高速缓存（200）的低压工作， 区域缓存（300）具有与高速缓存（200）不同的类型，高速缓存（200）和高速缓存（300）被独立地提供源电压; 高速缓存（200）可操作在低于高速缓存（300）可操作的下限电压的电压; 高速缓存控制单元（400）在允许仅高速缓存（200）操作的第一模式和允许高速缓存（200）或高速缓存（300）操作的第二模式之间操作可切换控制; 以及在所述第一模式下的所述高速缓存（200）工作以提供低于所述高速缓存（300）可操作的所述下限电压的电压，同时中断向所述高速缓存（300）的电力供应。

公开(公告)号：US09160361B2

公开(公告)日：2015-10-13

申请号：US13379271

申请日：2010-06-01

申请人： Hiroaki Inoue

发明人： Hiroaki Inoue

IPC分类号： H03M7/30

CPC分类号： H03M7/30 ,  H03M7/3086 ,  H03M7/6023

摘要： To provide a data compression method that can achieve a high data compression ratio and does not require a buffer circuit or only requires a buffer circuit having a small storage capacity at a receiving side. A data compressor device has an adjustment and compression tool operable to switch a plurality of code words having different code lengths and compress input data at a rate that does not exceed a predetermined receiving speed.

摘要翻译： 为了提供可以实现高数据压缩比并且不需要缓冲电路或仅需要在接收侧具有小存储容量的缓冲电路的数据压缩方法。 数据压缩装置具有可操作以切换具有不同代码长度的多个代码字的调整和压缩工具，并以不超过预定接收速度的速率压缩输入数据。

公开(公告)号：US09109344B2

公开(公告)日：2015-08-18

申请号：US13321599

申请日：2010-05-19

申请人： Kouya Iizuka ,  Satoru Nishimura ,  Hiroshi Yoshida ,  Hiroaki Inoue

发明人： Kouya Iizuka ,  Satoru Nishimura ,  Hiroshi Yoshida ,  Hiroaki Inoue

IPC分类号： E02F9/22 ,  E02F9/20 ,  F15B11/17

CPC分类号： E02F9/2004 ,  E02F9/2228 ,  E02F9/2282 ,  E02F9/2285 ,  E02F9/2292 ,  F15B11/17 ,  F15B2211/324 ,  F15B2211/526

摘要： In the working machine, first and second pilot flow paths are directly or indirectly connected to a tank flow path (52). A first restrictor is disposed between the first pilot flow path and the tank flow path. A second restrictor is disposed between the second pilot flow path and the tank flow path. An actuator control unit is configured to control an actuator based on a hydraulic pressure detected by a first hydraulic pressure detector unit and that detected by a second hydraulic pressure detector unit sensor.

摘要翻译： 在工作机器中，第一和第二先导流动路径直接或间接地连接到罐流动路径（52）。 第一限流器设置在第一先导流路和箱流路之间。 第二限流器设置在第二先导流路和罐流路之间。 执行器控制单元被配置为基于由第一液压检测器单元检测到的液压并且由第二液压检测器单元传感器检测到的液压来控制致动器。

公开(公告)号：US08473702B2

公开(公告)日：2013-06-25

申请号：US12602871

申请日：2008-06-05

申请人： Hiroaki Inoue ,  Tsuyoshi Abe ,  Junji Sakai ,  Masato Edahiro

发明人： Hiroaki Inoue ,  Tsuyoshi Abe ,  Junji Sakai ,  Masato Edahiro

IPC分类号： G06F12/00

CPC分类号： G06F9/44505 ,  G06F9/4856

摘要： Provided is an information processing device which enables transfer of an execution environment in a short time period without degrading basic performance of an execution environment and without requiring a large amount of memory.The information processing device comprises a basic side CPU 100 for executing basic processing and an addition side CPU 200 for executing additional processing, in which a transfer management unit 300 provided on the basic side CPU 100 transfers execution environment data 1000 including constitution information of an execution environment 30 of the additional processing to be executed on the addition side CPU and data in a memory corresponding to the execution environment to other information processing device and restores the execution environment to re-start the addition side CPU based on the received execution environment data 1000.

摘要翻译： 提供一种能够在短时间内传送执行环境而不降低执行环境的基本性能而不需要大量存储器的信息处理装置。 信息处理装置包括用于执行基本处理的基本侧CPU 100和用于执行附加处理的附加侧CPU200，其中设置在基本侧CPU 100上的传送管理单元300传送包括执行的结构信息的执行环境数据1000 在附加侧CPU执行的附加处理的环境30和与执行环境相对应的存储器中的数据到其他信息处理装置，并且基于接收到的执行环境数据1000恢复执行环境以重新启动加法侧CPU 。