公开(公告)号：US6147544A

公开(公告)日：2000-11-14

申请号：US270051

申请日：1999-03-16

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Masatoshi Ishikawa

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Masatoshi Ishikawa

IPC分类号： G11C11/417 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409 ,  G11C16/06 ,  H03K17/693 ,  H04L25/02 ,  H03K17/62 ,  H03K17/735 ,  H03K17/76

CPC分类号： H04L25/0272 ,  G11C7/1006 ,  G11C7/1012 ,  G11C7/1048 ,  H03K17/693 ,  H04L25/028 ,  H04L25/0292

摘要： First and second pairs of input/output lines transfer mutually complementary data signals respectively. First and second selection circuits select a signal transfer line having the same potential as that of a signal transfer line not precedently selected from two precedently selected signal transfer lines among first to third signal transfer lines and the signal transfer line not precedently selected and connect first ends thereof to the first pair of input/output lines respectively while connecting second ends thereof to the second pair of input/output lines respectively. Thus, no precharging may be performed for equalizing the potentials of the two signal transfer lines selected for present data transfer with each other, and hence reduction of a data transfer rate can be prevented.

摘要翻译： 第一和第二对输入/输出线分别传输互补的数据信号。 第一选择电路和第二选择电路选择与第一至第三信号传输线之间的两个先前选择的信号传送线之前未选择的信号传输线具有相同电位的信号传输线，并且先前选择信号传送线并且连接第一端 分别连接到第一对输入/输出线，同时分别将第二对输入/输出线的第二端连接到第二对输入/输出线。 因此，为了均衡用于当前数据传送选择的两个信号传送线的电位，可以不执行预充电，因此可以防止数据传送速率的降低。

公开(公告)号：US06384674B2

公开(公告)日：2002-05-07

申请号：US09353349

申请日：1999-07-15

申请人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Takaharu Tsuji

发明人： Hiroaki Tanizaki ,  Tsukasa Ooishi ,  Shigeki Tomishima ,  Masatoshi Ishikawa ,  Hideto Hidaka ,  Takaharu Tsuji

IPC分类号： G05F110

CPC分类号： G11C5/063 ,  G11C11/4074 ,  G11C11/4097 ,  H02J1/06

摘要： Provided is a power supply-to-power supply capacitance cell including a first capacitor connected between a sub power supply line and a sub ground line, a second capacitor connected between a main power supply line and the sub ground line, and a third capacitor connected between the sub power supply line and a main ground line. Thus, a voltage drop of the sub power supply line can be reduced in current consumption of an internal circuit, so that an operation of the internal circuit is stabilized and the operating speed thereof is improved.

摘要翻译： 提供了一种电源电源电容单元，包括连接在副电源线和副地线之间的第一电容器，连接在主电源线和副地线之间的第二电容器和连接在主电源线和副地线之间的第三电容器 在副电源线和主接地线之间。 因此，可以降低内部电路的电流消耗中的副电源线的电压降，使得内部电路的动作稳定，其运转速度提高。

公开(公告)号：US06885235B2

公开(公告)日：2005-04-26

申请号：US10095080

申请日：2002-03-12

申请人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

发明人： Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Hiroaki Tanizaki ,  Tsukasa Ooishi

IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/401 ,  G11C29/06 ,  G05F3/04

CPC分类号： G11C5/147

摘要： An internal power supply potential generation circuit includes an overcharge prevention circuit connected to an internal power supply node. The overcharge prevention circuit includes a circuit outputting a signal to be determined that is determined by an internal power supply potential, a differential amplification circuit amplifying a difference in potential between the signal to be determined and a reference potential for output to a node as a signal indicating that current should be drawn, and a current draw circuit drawing current from the internal power supply node in response to the signal indicating that current should be drawn. Thus the semiconductor integrated circuit device of interest can provide a steady internal power supply potential.

摘要翻译： 内部电源电位产生电路包括连接到内部电源节点的过充电防止电路。 过充电防止电路包括输出由内部电源电位确定的待确定信号的电路，放大要确定的信号之间的电位差和作为输出到节点的参考电位的差分放大电路作为信号 表示应该绘制电流，并且响应于指示应当绘制电流的信号，从内部电源节点抽出电流的电流绘制电路。 因此，感兴趣的半导体集成电路器件可以提供稳定的内部电源电位。

公开(公告)号：US06466509B1

公开(公告)日：2002-10-15

申请号：US10050131

申请日：2002-01-18

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C11/4087 ,  G11C2207/104

摘要： First and second memory banks are provided with M memory blocks each having first and second memory regions, M representing an even number of no less than two, and (M+1) sense amplifier bands arranged on opposite sides of each memory block, and have first and second select lines arranged therefor to select the first and second memory regions, respectively, the first select line being connected to an odd-numbered sense amplifier band of the first memory bank and an even-numbered sense amplifier band of the second memory bank, the second select line being connected to an even-numbered sense amplifier band of the first memory bank and an odd-numbered sense amplifier band of the second memory bank.

摘要翻译： 第一和第二存储体设置有M个存储块，每个存储块具有第一和第二存储区域，M表示偶数个不少于两个，以及（M + 1）个读出放大器频带，其布置在每个存储块的相对侧上，并具有 第一选择线和第二选择线分别用于选择第一和第二存储区，第一选择线连接到第一存储体的奇数读出放大器带和第二存储体的偶数读出放大器带 第二选择线连接到第一存储体的偶数读出放大器带和第二存储体的奇数读出放大器带。

公开(公告)号：US06411560B1

公开(公告)日：2002-06-25

申请号：US09987277

申请日：2001-11-14

申请人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Shigeki Tomishima ,  Mitsutaka Niiro ,  Masanao Maruta ,  Hiroshi Kato ,  Masatoshi Ishikawa ,  Takaharu Tsuji ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C514

CPC分类号： G11C7/1096 ,  G11C5/146 ,  G11C5/147 ,  G11C7/1078 ,  G11C7/22 ,  G11C8/10 ,  G11C11/4074

摘要： A first power supply voltage is supplied to a power supply node of a sense amplifier. A bit line driver outputs a column select signal composed of a second power supply voltage to the gate terminals of N channel MOS transistors of a GIO line gate circuit. When input/output data is [1], a third power supply voltage lower than the first power supply voltage is supplied onto a global data line. In this case, with a threshold voltage of N channel MOS transistors used, a relation is established: second power supply voltage≦third power supply voltage+threshold voltage. As a result, a leakage current can be reduced in a semiconductor memory device driven by plural power supply voltages with respective different voltage levels.

摘要翻译： 第一电源电压被提供给读出放大器的电源节点。 位线驱动器将由第二电源电压组成的列选择信号输出到GIO线路电路的N沟道MOS晶体管的栅极端子。 当输入/输出数据为[1]时，低于第一电源电压的第三电源电压被提供给全局数据线。 在这种情况下，利用所使用的N沟道MOS晶体管的阈值电压，建立关系：第二电源电压<=第三电源电压+阈值电压。 结果，在由具有不同电压电平的多个电源电压驱动的半导体存储器件中，可以减小泄漏电流。

公开(公告)号：US20060209585A1

公开(公告)日：2006-09-21

申请号：US11376202

申请日：2006-03-16

申请人： Hiroaki Tanizaki ,  Hideto Hidaka

发明人： Hiroaki Tanizaki ,  Hideto Hidaka

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2213/75 ,  G11C2213/76 ,  G11C2213/79

摘要： A path routing from a write current source supplying a write current through an internal data line, a bit line and a source line to a reference potential except a memory cell is configured to have a constant resistance independent of a memory cell position selected in a memory array, and each of the resistance value of the current path between the memory cell and the write current source and the resistance value of the current path between the selected memory cell and the reference potential node is set to 500Ω or lower. A nonvolatile semiconductor memory device having improved reliability of data read/write is achieved.

摘要翻译： 从写入电流源通过内部数据线，位线和源极线向除了存储器单元之外的参考电位提供写入电流源的路径被配置为具有独立于在存储器中选择的存储器单元位置的恒定电阻 阵列，并且存储单元和写入电流源之间的电流路径的电阻值和所选择的存储单元与参考电位节点之间的电流路径的电阻值中的每一个被设置为500Om以下。 实现了具有改善的数据读/写可靠性的非易失性半导体存储器件。

公开(公告)号：US20060152971A1

公开(公告)日：2006-07-13

申请号：US11374062

申请日：2006-03-14

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C11/14

CPC分类号： G11C11/15 ,  G11C11/16

摘要： During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

公开(公告)号：US06791876B2

公开(公告)日：2004-09-14

申请号：US10397352

申请日：2003-03-27

申请人： Hiroaki Tanizaki ,  Takaharu Tsuji ,  Hideto Hidaka

发明人： Hiroaki Tanizaki ,  Takaharu Tsuji ,  Hideto Hidaka

IPC分类号： G11C1100

CPC分类号： G11C11/16

摘要： A plurality of bit lines are divided into a plurality of groups each including Y (Y: integer of at least two) bit lines. Y data read data lines passing a data read current therethrough in data reading are provided along with Y connection control parts electrically coupling Y bit lines and the Y read data lines with each other every group. Therefore, the connection control parts electrically connected with the Y read data lines are uniformly divided so that parasitic capacitance applied to the read data lines following electrical connection with the connection control parts can be suppressed. Therefore, the time for charging the read data lines to a prescribed voltage level can be reduced for executing high-speed data reading.

摘要翻译： 多个位线被分成多个组，每组包括Y（Y：至少两个的整数）位线。 在数据读取中通过数据读取电流的Y数据读取数据线与Y个连接控制部分一起被提供，Y个连接控制部分将Y位线和Y个读取数据线彼此电组合。 因此，与Y读取数据线电连接的连接控制部分被均匀地分割，从而能够抑制与连接控制部件电连接之后的读取数据线路的寄生电容。 因此，为了执行高速数据读取，可以减少将读取数据线充电到规定电压电平的时间。

公开(公告)号：US6055206A

公开(公告)日：2000-04-25

申请号：US274623

申请日：1999-03-23

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi ,  Shigeki Tomishima

IPC分类号： G11C11/413 ,  G11C7/10 ,  G11C8/08 ,  G11C11/401 ,  G11C11/407 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1072

摘要： In a synchronous semiconductor memory device of the present invention, a main word driver and a sub decode driver have a function to take in a row decode signal in response to activation of a bank and to maintain the state of the row decode signal. Accordingly, of the circuits associated with row selection, a row pre-decoder, a row decoder and a row system control circuit can operate under a hierarchical power supply structure.

摘要翻译： 在本发明的同步半导体存储器件中，主字驱动器和子解码驱动器具有响应于存储体的激活而获取行解码信号并保持行解码信号的状态的功能。 因此，与行选择相关联的电路中，行预解码器，行解码器和行系统控制电路可以在分层电源结构下操作。

公开(公告)号：US07295465B2

公开(公告)日：2007-11-13

申请号：US11374062

申请日：2006-03-14

申请人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hiroaki Tanizaki ,  Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G11C11/14

CPC分类号： G11C11/15 ,  G11C11/16

摘要： During data reading, a sense enable signal is activated to start charging of a data line prior to formation of a current path including the data line and a selected memory cell in accordance with row and column selecting operations. Charging of the data line is completed early so that it is possible to reduce a time required from start of the data reading to such a state that a passing current difference between the data lines reaches a level corresponding to storage data of the selected memory cell, and the data reading can be performed fast.

摘要翻译： 在数据读取期间，根据行和列选择操作，激活感测使能信号以在形成包括数据线的当前路径和所选择的存储器单元之前开始数据线的充电。 早期完成数据线的充电，从而可以将开始数据读取所需的时间减少到数据线之间的通过电流差达到对应于所选存储单元的存储数据的电平的状态， 并且可以快速执行数据读取。