公开(公告)号：US20120018780A1

公开(公告)日：2012-01-26

申请号：US13075665

申请日：2011-03-30

申请人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

发明人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L27/11521

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 作为设置在相邻栅电极之间的隔离槽的内壁的一部分，包括平行于通过半导体基板上方的栅极绝缘膜设置的多个栅电极的沟道方向的侧面。 该方法可以包括形成覆盖栅电极的侧面的保护膜。 该方法可以包括使用栅电极作为掩模来蚀刻半导体衬底以形成隔离槽。 栅电极的侧面被保护膜覆盖。 该方法可以包括通过氧化隔离槽的表面来填充隔离槽的底部来形成第一绝缘膜。 此外，该方法可以包括在第一绝缘膜上形成第二绝缘膜以填充包括栅电极的侧面的隔离槽的上部。

公开(公告)号：US20120018783A1

公开(公告)日：2012-01-26

申请号：US13117525

申请日：2011-05-27

申请人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

发明人： Kazuaki Iwasawa ,  Shigeo Kondo ,  Hiroshi Akahori ,  Kiyohito Nishihara ,  Yingkang Zhang ,  Masaki Kondo ,  Hidenobu Nagashima ,  Takashi Ichikawa

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L29/1083 ,  H01L21/84 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/1207 ,  H01L29/66825 ,  H01L29/7881

摘要： According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode. In addition, the method can include filling an inside of the first isolation groove and an inside of the second isolation groove with a second insulating film.

摘要翻译： 根据一个实施例，公开了一种用于制造半导体器件的方法。 作为设置在相邻的栅电极之间的隔离槽的内壁的一部分，包括平行于设置在半导体基板上方的多个栅电极的沟道方向的侧面。 该方法可以包括形成穿过用作栅电极的导电膜的第一隔离槽，以到达半导体衬底。 该方法可以包括形成覆盖包括栅电极的侧面的第一隔离槽的侧壁的保护膜。 该方法可以包括通过蚀刻暴露于第一隔离槽的底表面的半导体衬底来形成第二隔离槽。 该方法可以包括氧化设置在栅电极的两侧的每一侧上的第二隔离槽的内表面，以形成第一绝缘膜，它们彼此连接在栅极下方。 此外，该方法可以包括用第二绝缘膜填充第一隔离槽的内部和第二隔离槽的内部。

公开(公告)号：US20120007163A1

公开(公告)日：2012-01-12

申请号：US13052531

申请日：2011-03-21

申请人： Hiroshi Akahori ,  Kiyohito Nishihara ,  Masaki Kondo ,  Yingkang Zhang ,  Shigeo Kondo ,  Hidenobu Nagashima ,  Kazuaki Iwasawa ,  Takashi Ichikawa

发明人： Hiroshi Akahori ,  Kiyohito Nishihara ,  Masaki Kondo ,  Yingkang Zhang ,  Shigeo Kondo ,  Hidenobu Nagashima ,  Kazuaki Iwasawa ,  Takashi Ichikawa

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L27/11521

摘要： According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.

摘要翻译： 根据一个实施例，非易失性存储器件包括衬底，第一和第二隧道绝缘膜，第一和第二浮栅电极，栅间绝缘膜和控制栅电极。 衬底具有通过元件隔离沟槽彼此隔离的第一和第二有源区。 第一和第二隧道绝缘膜分别位于第一和第二有源区中。 第一和第二浮栅电极分别位于第一和第二隧道绝缘膜上。 隔间绝缘膜包括第一绝缘材料的第一绝缘层，第一绝缘层上的第二绝缘材料的电子陷阱层和电子陷阱层上的第一绝缘材料的第二绝缘层。 控制栅电极位于隔间绝缘膜上。

公开(公告)号：US08723245B2

公开(公告)日：2014-05-13

申请号：US13052531

申请日：2011-03-21

申请人： Hiroshi Akahori ,  Kiyohito Nishihara ,  Masaki Kondo ,  Yingkang Zhang ,  Shigeo Kondo ,  Hidenobu Nagashima ,  Kazuaki Iwasawa ,  Takashi Ichikawa

发明人： Hiroshi Akahori ,  Kiyohito Nishihara ,  Masaki Kondo ,  Yingkang Zhang ,  Shigeo Kondo ,  Hidenobu Nagashima ,  Kazuaki Iwasawa ,  Takashi Ichikawa

IPC分类号： H01L29/788

CPC分类号： H01L29/7883 ,  H01L27/11521

摘要： According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.

摘要翻译： 根据一个实施例，非易失性存储器件包括衬底，第一和第二隧道绝缘膜，第一和第二浮栅电极，栅间绝缘膜和控制栅电极。 衬底具有通过元件隔离沟槽彼此隔离的第一和第二有源区。 第一和第二隧道绝缘膜分别位于第一和第二有源区中。 第一和第二浮栅电极分别位于第一和第二隧道绝缘膜上。 隔间绝缘膜包括第一绝缘材料的第一绝缘层，第一绝缘层上的第二绝缘材料的电子陷阱层和电子陷阱层上的第一绝缘材料的第二绝缘层。 控制栅电极位于隔间绝缘膜上。

公开(公告)号：US20110057249A1

公开(公告)日：2011-03-10

申请号：US12868450

申请日：2010-08-25

申请人： Takashi NAKAO ,  Kazuaki Iwasawa

发明人： Takashi NAKAO ,  Kazuaki Iwasawa

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L29/66477 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked structural body, a semiconductor pillar, and a memory unit. The stacked structural body is provided on a major surface of the substrate. The stacked structural body includes electrode films alternately stacked with inter-electrode insulating films in a direction perpendicular to the major surface. The pillar pierces the body in the direction. The memory unit is provided at an intersection between the pillar and the electrode films. The electrode films include at least one of amorphous silicon and polysilicon. The stacked structural body includes first and second regions. A distance from the second region to the substrate is greater than a distance from the first region to the substrate. A concentration of an additive included in the electrode film in the first region is different from that included in the electrode film in the second region.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括衬底，层叠结构体，半导体柱和存储单元。 层叠结构体设置在基板的主表面上。 叠层结构体包括在垂直于主表面的方向上交替层叠有电极间绝缘膜的电极膜。 支柱沿着方向刺穿身体。 存储单元设置在柱和电极膜之间的交点处。 电极膜包括非晶硅和多晶硅中的至少一种。 层叠结构体包括第一和第二区域。 从第二区域到基板的距离大于从第一区域到基板的距离。 包含在第一区域中的电极膜中的添加剂的浓度与第二区域中的电极膜中包含的添加剂的浓度不同。

公开(公告)号：US07803721B2

公开(公告)日：2010-09-28

申请号：US11685984

申请日：2007-03-14

申请人： Kazuaki Iwasawa

发明人： Kazuaki Iwasawa

IPC分类号： H01L21/469

CPC分类号： H01L21/3125 ,  H01L21/02164 ,  H01L21/02222 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02337 ,  H01L21/31612 ,  H01L27/115 ,  H01L27/11521 ,  Y10S438/906

摘要： A semiconductor device includes a deposited-type insulating film disposed on a substrate; a coating-type insulating film disposed on a surface of the deposited-type insulating film and having a film density which is lower than a film density of the deposited-type insulating film; and an intermediate insulating film disposed between the deposited-type insulating film and the coating-type insulating film and having a film density which is intermediate between the film density of the deposited-type insulating film and the film density of the coating-type insulating film.

摘要翻译： 半导体器件包括设置在基板上的沉积型绝缘膜; 设置在所述沉积型绝缘膜的表面上并具有低于所述沉积型绝缘膜的膜密度的膜密度的涂层型绝缘膜; 以及设置在所述沉积型绝缘膜和所述涂覆型绝缘膜之间并且具有介于所述沉积型绝缘膜的膜密度和所述涂覆型绝缘膜的膜密度之间的膜密度的中间绝缘膜 。

公开(公告)号：US20070103064A1

公开(公告)日：2007-05-10

申请号：US11643906

申请日：2006-12-22

申请人： Kazuaki Iwasawa ,  Hideki Ookawa

发明人： Kazuaki Iwasawa ,  Hideki Ookawa

IPC分类号： H05B33/00

CPC分类号： H01L51/5088 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/5048 ,  H01L2251/558

摘要： An electroluminescent display has a transparent substrate. A transparent positive electrode is formed on the transparent substrate. An inert metal film is formed on the transparent positive electrode. A hole transport layer on the inert metal film, includes a conductive polymer doped with a polymeric electrolyte containing a sulfone group. An emissive layer is formed on the hole transport layer.

摘要翻译： 电致发光显示器具有透明基板。 在透明基板上形成透明正极。 在透明正极上形成惰性金属膜。 惰性金属膜上的空穴传输层包括掺杂有含有砜基团的聚合物电解质的导电聚合物。 在空穴传输层上形成发光层。

公开(公告)号：US08329553B2

公开(公告)日：2012-12-11

申请号：US12730099

申请日：2010-03-23

申请人： Shogo Matsuo ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Kazuaki Iwasawa

发明人： Shogo Matsuo ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Kazuaki Iwasawa

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02343 ,  H01L21/3081 ,  H01L21/3124 ,  H01L21/3125 ,  H01L21/316 ,  H01L27/11531 ,  H01L27/11543 ,  H01L27/11548

摘要： A method for manufacturing semiconductor device has forming a plurality of trenches having at least two kinds of aspect ratios on a semiconductor substrate, filling the plurality of trenches with a coating material containing silicon, forming a mask on the coating material in a part of the trenches among the plurality of trenches filled with the coating material, implanting an ion for accelerating oxidation of the coating material into the coating material in the trenches on which the mask is not formed, forming a first insulating film by oxidizing the coating materials into which the ion is implanted, removing the coating material from the part of the trenches after removing the mask and forming a second insulating film in the part of the trenches from which the coating material is removed.

摘要翻译： 半导体器件的制造方法在半导体衬底上形成具有至少两种纵横比的多个沟槽，用包含硅的涂层材料填充多个沟槽，在沟槽的一部分中在涂层材料上形成掩模 在填充有涂层材料的多个沟槽中，将用于加速氧化涂层材料的离子注入到未形成掩模的沟槽中的涂层材料中，通过氧化其中离子的涂层材料形成第一绝缘膜 在移除掩模之后从沟槽的一部分去除涂层材料，并在去除涂层材料的沟槽部分中形成第二绝缘膜。

公开(公告)号：US20050052122A1

公开(公告)日：2005-03-10

申请号：US10895381

申请日：2004-07-21

申请人： Kazuaki Iwasawa ,  Hideki Ookawa

发明人： Kazuaki Iwasawa ,  Hideki Ookawa

IPC分类号： H01L51/50 ,  C09K11/06 ,  H01L51/00 ,  H05B33/00 ,  H05B33/14 ,  H05B33/22

CPC分类号： H01L51/5088 ,  H01L51/0034 ,  H01L51/0035 ,  H01L51/0037 ,  H01L51/5048 ,  H01L2251/558

摘要： An electroluminescent display has a transparent substrate. A transparent positive electrode is formed on the transparent substrate. An inert metal film is formed on the transparent positive electrode. A hole transport layer on the inert metal film, includes a conductive polymer doped with a polymeric electrolyte containing a sulfone group. An emissive layer is formed on the hole transport layer.

摘要翻译： 电致发光显示器具有透明基板。 在透明基板上形成透明正极。 在透明正极上形成惰性金属膜。 惰性金属膜上的空穴传输层包括掺杂有含有砜基团的聚合物电解质的导电聚合物。 在空穴传输层上形成发光层。

公开(公告)号：US20120034754A1

公开(公告)日：2012-02-09

申请号：US13272457

申请日：2011-10-13

申请人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

发明人： Kazuaki Iwasawa ,  Takeshi Hoshi ,  Keisuke Nakazawa ,  Shogo Matsuo ,  Takashi Nakao ,  Ryu Kato ,  Tetsuya Kai ,  Katsuyuki Sekine

IPC分类号： H01L21/76

CPC分类号： H01L21/76229

摘要： A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.

摘要翻译： 半导体器件制造方法在半导体衬底中具有形成元件隔离沟槽，在元件隔离沟槽的内部形成硅化合物膜，以便嵌入元件隔离沟槽，在第一温度下进行第一氧化处理以使表面 所述硅化合物膜能够通过氧化剂和杂质而不允许含有硅原子的挥发性物质通过的挥发性物质排放防止层，并且在比所述第一温度高的第二温度下进行第二氧化处理 温度以在元件隔离槽内形成被覆氧化硅膜。